1

I am working on a project in which the Makefile are used in haphazard manner. Project structure is shown as below

ProjectX ---- AppA
         ---- AppB
         ---- LibC
         ---- LibD
         ---- ToolE ---- AppF
                    ---- LibG

All these folders and sub-folders have their own Makefiles. They are invoked one by one from ProjectX, ToolE etc. In this setup, AppA may be dependent on LibC/LibD etc. But since they have different Makefile, the dependencies are not properly mentioned in the target recipe.

Now the problem at hand is that, I would like to make this project compile in parallel(make -jN)

I have tried generating the dependency files using gcc -M option and include ing these dependency files in the Makefile. But at times what I see is the only the .o are created but not the lib or the App. This may be because make sees the dependency and waits for the dependency to be ready. But doesn't know how to resume?

What is the best approach to fix this.

UPDATE

I understand that recursive make is a bad thing. But if you stuck with it due to legacy reasons, it's difficult to get the parallel make working.

For more on why recursive make is bad see this

Rohit Walavalkar
  • 790
  • 9
  • 28
  • 1
    Possible duplicate of [Makefiles with source files in different directories](https://stackoverflow.com/questions/1139271/makefiles-with-source-files-in-different-directories) – Iguananaut Oct 08 '19 at 12:24
  • There are several possible approaches. Which would you prefer, a simple adjustment or a really good approach that requires a major overhaul? – Beta Oct 08 '19 at 19:14
  • Thank you Iguananaut for pointing in the right direction. This answered all my queries http://aegis.sourceforge.net/auug97.pdf – Rohit Walavalkar Oct 09 '19 at 06:17

0 Answers0