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I read four double-precision 64-bit (qword) floats from memory into ymm1:

vmovupd ymm1,[r11+r15]

Now I want an instruction that converts them to integer. I tried the following:

VCVTTPD2UQQ ymm0,ymm1

OR

VCVTTSD2SI ymm0,ymm1

Both instructions assemble and link, but both crash at runtime.

All of my research points to these two instructions. Is there a different instruction I haven't found yet to convert four qword floats to qword integer in ymm registers?

Thanks for any help.

RTC222
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    The first is AVX512 (you can tell because it's doing packed double <-> 64-bit integer when AVX2 and earlier only have HW support for packed conversion to/from 32-bit integers). The 2nd isn't valid because it's `sd` (scalar double) with a ymm destination, not an integer reg like RAX. With NASM: `foo.asm:1: error: invalid combination of opcode and operands`. – Peter Cordes Oct 19 '19 at 20:45
  • Is there an instruction that will convert four floats in ymm to four integers to ymm? I can do it in four separate instructions using pinsrq, but I would like to do it with a single instruction, which I haven't found yet. – RTC222 Oct 19 '19 at 20:48
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    No, there isn't. AVX2 and earlier only have *packed* conversions to/from 32-bit integers, even for `double`. But fortunately a search for `site:stackoverflow.com double to 64-bit integer avx` found Mysticial's answer right away which explains all this. – Peter Cordes Oct 19 '19 at 20:49
  • That helps. He's using intrinsics, but I can translate. – RTC222 Oct 19 '19 at 20:50
  • Updated Mysticial's answer on the linked duplicate to state clearly that single-instruction support was new in AVX512. Note that I think he's converting with round-to-nearest, not truncation, so watch out for that. – Peter Cordes Oct 19 '19 at 20:57

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