Using command line input in makefile

Question

I currently have a makefile that when run will link a .h and .c file and then create a binary. Is it possible to make the makefile execute this binary by just doing make followed by an input file_name ?

My makefile looks something like this:

CC = g++
cppflags = "-std=c++0x"
all : interpreter

byte.o : opcode.h byte.h byte.cpp
    $(CC) -c $(cppflags) byte.cpp
interpreter : byte.o main.cpp
 $(CC) $(cppflags) byte.o main.cpp -o interpreter

If I do make I'll get an executable interpreter that takes the name of an input file as an argument. What I want to do is modify my makefile so that I can do make <file_name> making the makefile run the executable instead of having to use the binary created by the make I already have. The input file name can not be hard coded.

At first read, if I understand it, my answer is yes it is possible to do something like that.. I do it a lot. But on Linux, and the text to invoke your new app is specific to whether the app is local or in some other dir. — 2785528, Oct 30 '19 at 02:14

score 0 · Answer 1 · answered Oct 30 '19 at 04:57

0

Try this simple example:

  a : a.c
          gcc a.c -o a.o
          ./a.o
  b : b.c
          gcc b.c -o b.o
          ./b.o

when you run "make a", a.o executable. "make b", b.o executable.

answered Oct 30 '19 at 04:57

Hai

73
1
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score 0 · Answer 2 · answered Oct 30 '19 at 05:31

Usually, you invoke make on a target to create (e.g., make interpreter), and not on the input file (which make does not known how to build). One common way to address this is to define a (rule-based) target for executing the code. For example .res ('.res' for result). The target will run the program and save the output to the .res file.

You will invoke the target with make input_file_name.res

%.res: % interpreter
    interpreter $< > $@

Note explicit dependency to build interpret before running this target.

See make 'explicit' variables for more information on $< (input file), and $@ (output file)

score 0 · Answer 3 · answered Oct 31 '19 at 23:27

don't try to make make accept arguments other than targets to build.

instead create script:

#! /bin/sh
# rebuild if necessary
make
# run interpreter with arguments
interpreter "$@"

and run with arguments:

$ ./buildtheninterpret.sh filenametointerpret

for more explanation why do this and caveats of makefile hackery read my answer to another similar question: Passing arguments to "make run"

Using command line input in makefile

3 Answers3