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I'm new and I'm practicing computer science alone as a passion. In assembly a base pointer is used that allows me to refer to a specific memory location by subtracting a certain offset from the base pointer. What is obtained is the absolute address. EBP - offset = absolute address. But where is this subtraction performed?

in which register is the absolute address calculated?

I give a example of my confusion.

If I have MOV dword ptr[EBP], 10 in this case the value of EBP register represent the absolute address.

But if i have MOV dword ptr[EBP - 4], 10 in this case from the ebp address 4 bytes must be subtracted.

In which register is done this operation, where is written the result of this calculation?

Peter Cordes
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Tony92
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2 Answers2

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If you want the address calculation result in a register, use LEA instead of a load or store, or as well.

When used for actual memory access, address calculation happens inside an AGU in a load or store-address execution unit and is not written back to an architectural register. It's only passed on to the TLB for translation to physical then written to the store buffer. (Or for a load, used to probe L1d cache). This internal addition has some latency and Intel CPUs even try to skip it in some cases, leading to having to replay the uop if they guess wrong. (Is there a penalty when base+offset is in a different page than the base?)

Unlike ARM or a few other ISAs, x86 does not have any addressing modes that write the final address back to the base register.

CPUs are made of a lot of transistors. Some of them are for internal buffers and adders separate from the named registers. The point of addressing modes beyond [reg] is that you can use them without modifying any of the values you currently have in registers.

Peter Cordes
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  • Thanks to you I discovered the Address generation unit. So is it within this unit that all the arithmetic operations for calculating the absolute address are done? Is the AGU involved even when the address only needs to be calculated, but there is no need to access the memory, as in the case of LEA? – Tony92 Nov 20 '19 at 16:13
  • @Tony92: in a few CPUs (like in-order Atom) yes. Otherwise no, LEA runs on ALU execution units like the shift-and-add instruction it is, on all out-of-order execution x86 CPUs, so it doesn't compete with actual loads. See https://agner.org/optimize/ for instruction tables and a microarch guide. Also https://stackoverflow.com/tags/x86/info for more links. – Peter Cordes Nov 20 '19 at 16:34
  • The thing i can't understand [ebp - 4], where is the calculation of the address done in ALU or AGU ? if I use MOV (where there is access to memory) the address is calcutated by AGU, if I use LEA (where there is no access to memory) the address is calculated by ALU ? – Tony92 Nov 20 '19 at 16:47
  • @Tony92: different microarchitectures implement it differently. Original 8086 was internally microcoded and not pipelined, and didn't have a dedicated AGU. Many in-order uarches run LEA on AGU hardware. Most out-of-order uarches run LEA on ALU execution units, like any other shift or add instruction. But AMD K8/K10 run it on AGU units. See comments on [LEA or ADD instruction?](//stackoverflow.com/posts/comments/55324794). There's no software-visible difference, only performance tuning considerations and "fun fact" how CPUs work under the hood knowledge. – Peter Cordes Nov 20 '19 at 22:48
  • @Tony92: But if it helps you remember what LEA does, then yeah think of LEA as just another ALU instruction, different from memory access through an AGU. – Peter Cordes Nov 20 '19 at 22:49
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As Jester said, it's not user visible.

Most processors have multiple registers, called a register array, that hold data and instructions that must be accessed rapidly during the execution of an application. One of them is the Memory address register (MAR)

the CPU uses the MAR to store the address to which these data will be placed on the system RAM, or where they will be accessed from.

PS: as I'm not a native english speaker I'm not 100% sure it answer your question

Community
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MrHeliose
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  • That's how a toy CPU without virtual memory would work, yes. But for example Ice Lake can do 2 loads and 2 stores per clock with its multi-ported cache. A store-address uop just writes the physical address into the store buffer, for later use if/when the store instruction retires (becomes non-speculative). See [x86 registers: MBR/MDR and instruction registers](//stackoverflow.com/q/51522368) - real x86 CPUs don't have anything as simple as a single MAR, and of course they have cache. – Peter Cordes Nov 20 '19 at 16:37
  • Well as far as i know, MAR are still in use... no? [link](https://web.archive.org/web/20170328171842/https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Overall/mar.html) – MrHeliose Nov 20 '19 at 17:04
  • Taking Sandybridge-family / Skylake-client as an example, if a load misses in private L1d and L2, then a request for the whole cache line goes over the ring bus to a slice of L3. If that misses, then the request goes over the ring bus to one of the DDR4 memory controllers. DDR SDRAM addressing doesn't put the whole address on any specific bus at once; it breaks it down into row/column. After sending a row-select command, the memory controller issues a read-burst command with the column address on the address lines https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory#Commands – Peter Cordes Nov 20 '19 at 22:39
  • So there isn't physically a full-width external "address bus"; there are 64 parallel data lines so a burst of 8x 8-bytes fills a cache line, but addresses are split. See also [What Every Programmer Should Know About Memory](https://www.akkadia.org/drepper/cpumemory.pdf) for more details of DDR SDRAM. Of course components that track in-flight load and store requests have to keep track of the address somehow, but it's not useful or interesting to call every address buffer a MAR because they're generally *not* directly connected to any "address bus". – Peter Cordes Nov 20 '19 at 22:44