I have this code:
mov rax, 0x93f3ffc2fbc7a1ce
mov rbx, 0x5862d8a05a385cbe
imul eax, ebx
How does imul work for 64-bit assembly? Will the overflow aex be written in the first 32 bits of rax?
I have this code:
mov rax, 0x93f3ffc2fbc7a1ce
mov rbx, 0x5862d8a05a385cbe
imul eax, ebx
How does imul work for 64-bit assembly? Will the overflow aex be written in the first 32 bits of rax?
Your code assembles to
0: 48 b8 ce a1 c7 fb c2 movabs rax,0x93f3ffc2fbc7a1ce
7: ff f3 93
a: 48 bb be 5c 38 5a a0 movabs rbx,0x5862d8a05a385cbe
11: d8 62 58
14: 0f af c3 imul eax,ebx
which uses the opcode 0F AF
for imul
. This instruction has 32-bit operand size so it only read EAX and EBX, and only writes EAX. This implicitly zero-extends into RAX, zeroing the upper 32 bits.
Unlike the 1-operand form of imul
, the high-half of the 32x32 => 64-bit full multiply isn't written to EDX (or anywhere else like the high half of RAX); it's simply discarded or for efficiency not even calculated at all. See the documentation; 2-operand imul reg, r/m32
is just like add reg, r/m32
or or reg, r/m32
- it doesn't do any special weird stuff.
Using mov rax, imm64
before this 32-bit multiply is completely pointless, mov eax,0xfbc7a1ce
would give exactly identical results. (The imul
doesn't destroy RBX, so the upper 32 bits of the value you put into RBX is still there if you want to read it later. It has no effect on the imul
instruction, though.)
Even better, imul eax, ebx, 0xfbc7a1ce
could have avoided a mov
.