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Description of this instruction is:

Signed divide EDX:EAX by DWORD byte (EAX=Quo, EDX=Rem)

I don't understand what : means here? Whats the meaning of EDX:EAX?

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    it is a 64 bit number upper bits are EDX lower are EAX – old_timer Jan 31 '20 at 19:56
  • its a 64 bit number divided by a 32 bit number and then you get a 32 bit quotient and 32 bit remainder. – old_timer Jan 31 '20 at 19:57
  • To add to the above comments, in case it wasn't obvious, `idivl` = `i` - integer (signed), `div` - divide, `l` - long. Divides a long (64-bit) signed integer. – J... Jan 31 '20 at 20:13
  • are you creating [2 accounts](https://stackoverflow.com/users/12822199/josh) just for asking 2 questions? – phuclv Feb 01 '20 at 01:29
  • From the [Intel® 64 and IA-32 Architectures Software Developer’s Manual](https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4): *3.7.2 Register Operands: [...] Some instructions (such as the DIV and MUL instructions) use quadword operands contained in a pair of 32-bit registers. **Register pairs are represented with a colon separating them.** For example, in the register pair EDX:EAX, EDX contains the high order bits and EAX contains the low order bits of a quadword operand.* – phuclv Feb 01 '20 at 02:08

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Following the comment from this question

Because the instruction was introduced on a 32-bit architecture. It divides a 64-bit value in EDX:EAX by a 32-bit value, the result is stored in EAX for the Quotient, and EDX for the Remainder. On the 32-bit architecture there were no 64-bit registers like RAX

See comment here

Febriyanto Nugroho
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