I understand that the reorder buffer can be used as an history buffer for speculative execution needs, and it also allows registers to be renamed into ROB entries (to break named dependencies, as register renaming).
Reading resources/manuals online, it would seem that the store buffer is also used for speculative execution. Isn't the ROB sufficient to discard values in case of a wrong path prediction?
Everything is treated as speculative until it reaches retirement - in-order retirement is how CPUs check for exceptions that should have happened before execution reached some later-executed instruction. And branch mispredicts, etc. So yes to both.
Isn't the ROB sufficient to discard values in case of a wrong path prediction?
No, register renaming only handles registers, not values to be stored to memory.
You need a store buffer so you can execute stores early without making potential mis-speculation visible to other cores! Otherwise stores would have to wait until they reached the in-order-retirement stage so they were known to be non-speculative before they could even execute. (And the cache line would have to be present in Exclusive or Modified state).
A store buffer is also valuable to decouple execution from cache misses; no need to wait until a cache line arrives if you can just leave it in the store buffer. This applies even to in-order pipelines. And it works for OoO exec even beyond retirement, so cache-miss stores have a larger window to not stall the pipeline, not tied to in-order retirement order.
More detail: Can a speculatively executed CPU branch contain opcodes that access RAM?
Related: Size of store buffers on Intel hardware? What exactly is a store buffer? and probably a bunch of other SO answers I've written. https://stackoverflow.com/search?q=user%3A224132+%5Bcpu-architecture%5D+store+buffer
it also allows registers to be renamed into ROB entries
sounds like you're talking about an implementation detail of Intel's P6 family. Most other designs (Sandybridge-family, and AMD) use a separate physical register file (PRF), and the ROB only has pointers to PRF entries. This makes more sense for a 64-bit architecture where the size of a register is larger, especially when we consider 128-bit XMM registers.
See https://www.realworldtech.com/sandy-bridge/ - SnB was the major change from P6 family to SnB-family.
