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I'm working with an FPGA that has a 40-pin bidirectional parallel port. To set the direction of the pins, I need to change the value of memory location 0xFF200074 to 0x0000FFFF. However, when I try to MOV #0x0000FFFF into a register, I get an error saying it's too large. I'm trying to move that value into the register so I can subsequently STR it into memory.

I don't believe I'm able to manipulate memory directly with ARM. But there must be an easy way to do this and I am just not seeing it.

Ryan Oliver Lanham
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    You need to load that constant from memory as the instruction does not have enough space for arbitrary immediates. You can use `ldr r0, =0x0000FFFF` to let your tools handle it for you. – Jester Mar 19 '20 at 19:59
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    Ask a compiler to compile `*foo = 0xffff` for you, in a function that takes a pointer arg. Then look at the optimized asm output. If you use `-mcpu=` an ARMv7 CPU, it can use `movw` to create that bit-pattern in one instruction. – Peter Cordes Mar 19 '20 at 20:02
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    this has unfortunately (or not depending on the view) been asked and answered many times here. Should be able to find them. If you look at the instruction set you can see how and why. you can build any number from four instructions using armv4 (armv1/2/3?) instructions, can load from a nearby pool with one instruction and a pool. as mentioned with newer cores you can do it in fewer instructions. not all but some assemblers support the ldr r0, = 0x12345678 syntax and will supply the solution for you, that is often the goto unless your assembler doesnt support it – old_timer Mar 19 '20 at 21:22
  • If you can't do it in one instruction use two or more... – Erik Eidt Mar 19 '20 at 21:57
  • There are multiple ways to do this. You have two RISC concepts. One is [arm constants](https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/how-to-load-constants-in-assembly-for-arm-architecture) due to symmetric op-code sizing. The other is load/store CPU. What you can do with load/store on RISC is limited by **DESIGN**. It makes the CPU less complex. – artless noise Mar 21 '20 at 13:22

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