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Consider a system where with 32 bits for adress .6 bits are used for segment so we have 2^6=254 segments.14 bits are used for paging= so we have 2^14= 16K pages.12 bits are used offset= so we have 2^12=4KB page size.My question is what is the maximum physical memory that can be supported by the system? A solution i am considering is that If a page table entry is 32-bit long it can give 32 bits to use as the high part of the physical address. So the maximum phyiscal memory that can be supported will be 2^32*2^14=2^46 but i have no idea if thats correct i mean segments don't play

SteliosE
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Phys address size is not uniquely determined by virtual address size and page size.

Instead the upper limit of physical memory size for an ISA is determined by the page size and the number of physical page-address bits in a page-table entry.

For example, x86-64 (and x86 32-bit with PAE) have PTEs with room for 52-bit physical page-frame addresses.

The PTE itself has 40 of those bits, and the low 12 have to be 0 (page-frames are naturally aligned). x86 / x86-64 uses 4k pages = 12 bits for the byte-within-page part of physical and virtual addresse. Why in 64bit the virtual address are 4 bits short (48bit long) compared with the physical address (52 bit long)? has diagrams of the format and some nice explanation.

The architects of that page-table format chose to align the page-number bitfield so it starts at bit #12, with bits 11:0 holding flags. So the position of the top of the field is the physical address width. If they had more or fewer flags than page-offset bits, that wouldn't be the case.

In practice real hardware might only implement some lower number of physical bits. For example, my i7-6700k desktop Skylake reports (via CPUID) that it implement 39-bit physical addresses (and 48-bit virtual). In that case the higher bits above 39 in a page-table entry are reserved.

(Fewer physical bits supported means smaller cache tags, and smaller TLB entries, among other things.)

Fun fact: PML5 extends x86-64's paging scheme from 4 levels (48-bit virtual) to 5-level (57-bit virtual) with no change in physical address width. That's another good reminder that physical and virtual address width are independent.

Also note that not having enough virtual address space to map all the RAM makes it really inconvenient to write an OS. Linus Torvalds wrote an entertaining and informative rant about PAE (wide physical addresses for 32-bit virtual addresses on 32-bit x86), quoted on someone's blog.

Your 32-bit virtual space for 44-bit physical would be really hard for an OS to use.

Peter Cordes
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  • So as you said,upper limit of physical memory size is determined by the page size and the number of physical page-address bits in a page-table entry.So in my case where a PTE can hold 32 bits the maximum physical memory that can be supported is 2^32*2^12(page of size)=2^44? – SteliosE Apr 12 '20 at 07:34
  • @SteliosE: I guess so, but only if literally all the bits of a PTE are page-number bits, with no present / absent or permission flags. That would mostly defeat the purpose of paging, and an OS would have to provide a complete page table to every process. "unused" virtual pages could all be mapped to the same physical page, but every process would need 2^14 times 32-bit PTEs, or 64kiB of PTEs. That's less than I though because you use 6 bits for segments. (2^6 = 64, not 254). But still an implausible design. – Peter Cordes Apr 12 '20 at 08:18