Can memory address be loaded in a cache but not in the main memory? In other words, if cache wants to write data into the main memory, can that generate page fault in x86-64 with Linux?
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No, cache is transparent (and in x86-64 caches by physical address). Only load or store instructions (and code-fetch) can page fault, and that happens synchronously (on the offending instruction), not some random time later.
Of course, actual commit to L1d cache is delayed (by the store buffer) until after retirement from the out-of-order execution back-end. But checking for faults is done in the load/store execution unit (which for stores, writes data and address into the store buffer for it to definitely happen and become visible some time later.)
Peter Cordes
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Technically, a memory access could complete before the page was returned to memory (or paged-out memory) or allocated/zeroed (for new memory). The Mill's backless memory does this for unallocated pages (reads provide a zero cache block, writes write into cache (which is virtually addressed). This is "easy" for zero copy-on-write pages, for swapped pages interleaving as the swapped data becomes available would be more complex (but still doable). Even with a physically tagged cache, one could use "shadow pages" to for tagging. – Feb 16 '21 at 15:15
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@PaulA.Clayton: Interesting, I'll have to read up on that sometime. One could also mention x86's "cache as ram" / "no fill" mode, but that doesn't apply to the "normal program running" use-case, while The Mill does speed up normal programs with that trick. – Peter Cordes Feb 16 '21 at 15:19
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@PaulA.Clayton: unrelated, you probably already saw this recent cpu-architecture question, but if not, I'd be interested in your feedback on my guesswork in [How do weak ISAs resolve WAW memory hazards using the store buffer?](https://stackoverflow.com/q/66224125). (This comment will self-destruct). – Peter Cordes Feb 16 '21 at 15:20