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Well, I just recently started reading the book: Structured Computer Organization, By Andrew Tannerbaun, and everthing was clear to me until I reached this sentence on ch.2: "Finally, many computers can transfer 64 or 128 bits in parallel on a single bus cycle, even on 32-bit machines". The problem with this is that I cannot picture how something like this would work and, as far as I know, a cpu has a single data bus. If there were for example, a 32bit CPU in a 64bit system (64bit data bus), how would the CPU do to transfer the 64bits "in parallel" on the same bus cycle?

Peter Cordes
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Luis Balza
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    By having wider and/or double-data-rate buses to fill a whole cache line in a few cycles. CPU bitness is not the bus width. Different parts of CPUs can have different widths, and deciding which one you use to describe the CPU is mostly a pointless exercise, although often register width or address width are chosen in modern CPUs. – Peter Cordes May 24 '20 at 03:49
  • See also [What Every Programmer Should Know About Memory?](https://stackoverflow.com/q/8126311). BTW, older CPUs without cache did often use the bus width as the bitness of the CPU, but cache decouples execution from memory. Also related: [How can cache be that fast?](https://electronics.stackexchange.com/q/329789) – Peter Cordes May 24 '20 at 04:01

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