How to enlarge bus width using Vitis libraries BLAS

Question

I am trying to use the BLAS L1 implementation from Vitis libraries, I want to set bus width to 128 bit, I am doing it using the ap_int.h header, defining an ap_int<128> structure.

I implemented an OpenCl kernel with VITIS HLS module, but the returned result is wrong (it works well for int32_t* type as input vector)

#include "ap_int.h"
#include <hls_stream.h>
#include "xf_blas.hpp"


using namespace xf::blas;

extern "C" {

void min_kernel(ap_int<128>* inVec,
                int* resultIndex, // index of the minimal item in the vector
                int p_n)
{
#pragma HLS INTERFACE m_axi port = inVec offset = slave bundle = gmem
#pragma HLS INTERFACE m_axi port = resultIndex offset = slave bundle = gmem

#pragma HLS INTERFACE s_axilite port = inVec bundle = control
#pragma HLS INTERFACE s_axilite port = resultIndex bundle = control
#pragma HLS INTERFACE s_axilite port = p_n bundle = control
#pragma HLS INTERFACE s_axilite port = return bundle = control

        int res;

        hls::stream<WideType<ap_int<128>, 1 << 2> > l_str;
    #pragma HLS data_pack variable = l_str
    #pragma HLS DATAFLOW
        readVec2Stream<ap_int<128>, 1 << 2>(inVec, p_n, l_str);
        amin<ap_int<128>, 2, int>(p_n, l_str, res);
        *resultIndex = res;
}
}

Is there another way to set the bus width or define the parallely processed entries - in the amin function?

How to enlarge bus width using Vitis libraries BLAS

0 Answers0