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I was asked this question in an interview related to COMPUTER ARCHITECTURE. Given an L1 cache, i can read and write into the cache and assuming it to be byte addressable and L2 and memory cache to be present in further hierarchy.

Describe an algorithm to find size of given cache

This was the only info given to me. Please tell me if I am missing any info/assumptions here.

Thanks

Peter Cordes
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Ashlesha Sunil Agate
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  • Usually you look for memcpy / memset bandwidth vs. buffer size and notice performance fall off in a stair-step. The first drop is the limit of L1 size, next drop is L2 size. I found a duplicate which shows this. Or with latency, pointer-chasing through linked lists. TLB effects can be a complication. – Peter Cordes Jun 26 '20 at 02:49
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    @Peter - the signal is much stronger with latency. Some chips (eg ARM N1) hace basically flat bandwidth from L1 through RAM, so it is very hard to pick out the cache levels from a bandwidth measurement. Nothing requires outer cache levels to have lower bandwidth than inner, but latency is almost certainly quite different. TLB is an issue as you point out. – BeeOnRope Jun 26 '20 at 18:17

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