2

I have an Intel(R) Core(TM) i7-4720HQ CPU @ 2.60GHz (Haswell). The chipset datasheets include Datasheet, volume 1 (M- and H-processor lines) and Datasheet, volume 2 (M- and H-processor lines). The physical address mapping is as follows: enter image description here I want to know which bits of the physical address determine the target rank and channel. Based on Volume 2, if high-order rank-interleaving is enabled, either of the address bits 20-27 can be used: enter image description here Does this mean that if I used high-order rank-interleaving, I can choose the rank bit, and, otherwise, the rank bit should be detected using reverse-engineering? How about the channel bits?

P.S.: The chipset supports two channels, each supporting up to two DIMMs, each supporing up to two ranks.

TheAhmad
  • 810
  • 1
  • 9
  • 21
  • 2
    Sorry, I'm in a bit of a hurry. Meanwhile, see [this](https://os.itec.kit.edu/downloads/publ_2017_hillenbrand_xeon_decoding.pdf). – Margaret Bloom Jul 11 '20 at 19:36
  • Thanks! I will check that. But I have a *Laptop* `Haswell` processor. Will `Xeon` *physical memory address layout* match that? – TheAhmad Jul 14 '20 at 15:35
  • 2
    mmm, probably not. The big difference is that your laptop is single-socket, so the whole SAD this is not used. You can use that PDF as a starting point but nothing more. The exact mapping is not public and must be reverse-engineered. It's not trivial :( – Margaret Bloom Jul 14 '20 at 17:11

0 Answers0