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I am trying to read Intel software developer manual to gain some understanding how operating system works and these four addressing terms is confusing me . Here is what i have understood, correct me if I am wrong.

linear address : What appear to a isolated program a long string of memory which start with address 0. all the segment of that program will be addressed from its linear address. It may be in the ram or in the disk.

physical address : Address that appear in the ram or main memory pins .

logical address : Combination of swap memory in the disk and ram . All the linear memory for all the program will stay in logical address space.It can be only used by kernel mode. The translation from logical to physical address is done by internal hardware.

virtual address : Virtual address is same as linear address. It will be only used by user mode in the operating system. Operating system will map virtual address from logical address.

ase
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NomanMahdi
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    Intel manuals won't talk about swap space directly. Mapping a process's virtual address space to physical pages or RAM or paging them out to disk is an OS thing, and AFAIK it's not typical to talk about the combination of physical RAM + swap as a single address space. – Peter Cordes Jul 20 '20 at 15:01
  • Semi-related: [Where is the Linear Address Space located?](https://stackoverflow.com/q/62585751) – Peter Cordes Jul 20 '20 at 15:01

2 Answers2

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The linear address space denotes all addresses that can be formed on the system. An address for any byte in linear address space is called a linear address. Todays system have around 46 bits of memory bus width, which corresponds to a linear address space of around 64 TiB. Intel only uses this term in its flat memory model.

The memory that the processor addresses on its bus is called physical memory. Each byte is assigned a unique address, called a physical address. It should be noted that in addition to the memory, memory-mapped I/O devices are also connected to this bus and can be addressed. This memory area also does not have to be contiguous, the memory controller here assigns the physical addresses to individual memory bars and devices.

Paging now adds virtual address spaces: each program is assigned its own linear address space. Some addresses in this address space are valid, others are not. valid addresses refer to data that may be in the physical memory but also to outsourced data on a hard disk (swap files). The translation is done in hardware by the MMU (Memory Management Unit) together with the TLB (Translation Lookup Buffer) or by the operating system. It is also possible that this data does not exist at all and is only generated when accessed, but this leads too far here. Let us note that these are the virtual addresses.

Logical addresses are a term that intel uses in the segmented memory model: there the memory is divided into segments. To address a byte in a segment, a logical address is used. This consists of a segment selector and an offset. Logical addresses are converted into virtual addresses using the segment selectors: The selector contains the beginning of the segment and its size. If the offset is larger than the size of the segment, the address is invalid. Adding the beginning of the segment to the offset gives you the virtual address. This segmented memory model was largely abolished in 64bit mode.

Summary

Logical Addresses -> Virtual Addresses -> Physikal Addresses

Virtual addresses and physical addresses are linear addresses, but not the other way around.

References:

fcdt
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    To go a step further and address a misconception from the question: physical addresses do *not* appear directly on external pins. (And not just because of how the integrated DDR4 memory controllers work by sending addresses as separate row/column.) As you point out, there is a mapping from physical address space to MMIO and RAM. Systems with dual-channel memory controllers alternate between channels for adjacent cache lines (or some other granularity?) of physical RAM, improving bandwidth for a single contiguous stream. – Peter Cordes Jul 20 '20 at 15:07
  • I completely skipped the cache here too. – fcdt Jul 20 '20 at 15:08
  • Sure, but cache is transparent (enough), only hiding the low 6 bits of physical addresses (offset-within-line) from the rest of the system. And then only for cacheable accesses; uncacheable loads / stores are possible at any time if you have a UC mapping, and/or cache can be disabled. – Peter Cordes Jul 20 '20 at 15:10
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    Also, "linear address" has a specific technical meaning in x86 terminology, as the result of `seg:off` -> `seg_base + offset`. My understanding was that with paging enabled, linear address = virtual address, and *then* translation to physical is another step. The fact that virtual and physical address spaces can be described as linear (using the common English / computing meaning of the word) is a separate thing. But I haven't actually read what Intel has to say about that recently so IDK if I'm inventing that terminology. – Peter Cordes Jul 20 '20 at 15:14
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    @Peter Cordes: I also use linear as the result of the segmented address computation. Segmented to linear and virtual to physical are two separate steps. – ecm Jul 20 '20 at 15:25
  • Thanks this is the answer, i was looking for. The last confusion I have is you said logical address is combination of the segment selector and the offset. Those segment selector address is using which address space physical or logical address? – NomanMahdi Jul 20 '20 at 15:26
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    @NomanMahdi2424: seg:off (logical) to linear happens *before* virt->phys translation, so the segment base is a virtual address. (Note that only FS and GS can have non-zero segment bases). More normally you just think of the offset (i.e. the "normal" part of an address, like `[rdi]`) *as* a virtual address, because even in 32-bit mode a flat memory (segment base=0) is standard. – Peter Cordes Jul 20 '20 at 15:27
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Isn't that to every process is given by OS a virtual address space 4GB or something. Than this addresses are translated by compilers to logical addresses which is a CPU terminology independent of any OS implementation. So I think the correct sequence is:

Virtual -> Logical -> Linear -> Physical
baz
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  • Virtual and linear are the same thing (when paging is enabled), so no. You don't start with a virtual address in 32-bit x86, you start with a segment base and an "effective address" (offset). Compilers don't translate addresses either, they just make code. Linkers may fill in absolute addresses into some locations, but that happens before run-time. – Peter Cordes Jul 24 '21 at 20:22
  • Yes, I'm fully sure that seg:off -> linear happens first, and that linear addresses *are* virtual, i.e. the input to virt->phys translation via page tables, when paging is enabled. See how https://wiki.osdev.org/Global_Descriptor_Table uses the term "linear address" for example to talk about virtual addresses of the GDT itself, or of segment bases, when paging is enabled. In real mode, or with paging disabled in other modes where that's possible, linear addresses are physical. – Peter Cordes Jul 25 '21 at 10:27
  • See also [Linear address and physical address](https://stackoverflow.com/q/4202669) / [What are the differences among flat address space,linear addresses,base address,effective address calculations](https://stackoverflow.com/q/58517521) / [Where is the Linear Address Space located?](https://stackoverflow.com/q/62585751) / [Why in x86-64 the virtual address are 4 bits shorter than physical (48 bits vs. 52 long)?](https://stackoverflow.com/q/46509152). Or read Intel's manuals, although they're really big. – Peter Cordes Jul 25 '21 at 10:32