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I am inclined to believe data is delivered in register widths so interleaving never happens when two processors read/write the same memory. I hope to eliminate the need for lock, mutex, or other protection since it doesn't matter which value is there to the reading process, as long as it is one or the other and not partially one and the other.

Does anyone know documentation proving it one way or the other?

Peter Cordes
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jlettvin
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    *aligned* load/store with size 1, 2, 4, or 8 bytes are guaranteed atomic on x86 - you definitely always get one value or the other, not tearing / interleaving. On Intel specifically, atomic as long as it doesn't cross a cache-line boundary. To take advantage of this from languages other than asm, you need C++11 `std::atomic<>` with memory_order_relaxed (or acquire and release). – Peter Cordes Aug 28 '20 at 01:03
  • Thank you for the pointer. It's a shame I can't upvote it. – jlettvin Aug 29 '20 at 15:22
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    You should be able to upvote my answer on the linked duplicate, [Why is integer assignment on a naturally aligned variable atomic on x86?](https://stackoverflow.com/q/36624881) if you want. If any of the other answers I linked in that answer are helpful, you can upvote them, too. See also https://stackoverflow.com/tags/x86/info for more links to docs / manuals, guides, and Q&As. – Peter Cordes Aug 29 '20 at 15:23
  • Thank you again. Love the stackoverflow x86 url. I used to use iAPX86 assembly language only for a good few years as I wrote one of the first PC antiviruses for Lotus. I already knew about the alignment (thanks), but my knowledge was from the bygone era of SISD, and I worried that memory architecture had changed to cope with multiple cores and that interleaving may have crept in. – jlettvin Aug 30 '20 at 16:43

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