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VAX CPUs has a updateable microcode feature. User can reupload microcode to VAX machine and then CPU will behave as not VAX CPU, but e.g. as PDP11 CPU.

What CPUs can be simulated with VAX microcode? Can it run machine code from a 6502, 8080, 8086?

My question is not about software simulators (like SIMH or qemu; there was an Alpha software simulator, speeded up by some microcode update), but about hardware microcode; both about theoretical possibility of making such microcode and practical microcode versions.

osgx
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    Some of the early machines had support for user writeable microstore, e.g. the 11/780. I don't recall any of the MicroVAXen being microcoded, nor do I recall anyone trying to make it into a different machine. See http://en.wikipedia.org/wiki/Microcode#Writable_control_stores . – HABO Aug 18 '11 at 02:13
  • user92546, do you know any popular microcode version, which will emulate non-vax CPU on VAX? – osgx Aug 18 '11 at 03:47
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    [VAX-11/780 Microprogramming Tools User's Guide](http://bitsavers.org/pdf/dec/vax/780/AA-H306B_780uprogToolsMar82.pdf) "explains" how to generate and use microcode for the Extended WCS which is an additional WCS memory card that allows customers to add microcode that can be invoked by the Extended Function Call (`XFC`) instruction. AFAIK, there was no support for customers altering the standard microcode for the VAX instruction set. – HABO Dec 20 '20 at 03:14
  • here's a wayback link for the [VAX-11/780 Microprogramming Tools User's Guide](https://web.archive.org/web/20190725113840/http://bitsavers.org/pdf/dec/vax/780/AA-H306B_780uprogToolsMar82.pdf) that works ... – davidbak Mar 19 '22 at 01:32

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I believe RAM-based changeable VAX microcode storage area ("WCS", writeable control store) did not allow enough space for a whole new instruction set to be defined.

At best it would allow a few new instructions to be added or for a bug fix for a problematic instruction - a la today's microcode updates for X86 CPUs.

For a complete instruction set it would likely require new microcode ROM/PLA devices and that could well require special gate arrays, esp for the later VAX 8xxx CPUs.

Since (besides desktop VAXen which were later MIPS RISC boxes) these were expensive 'big iron' machines used in an IT context - I don't see them ever having been used in such a 'dreamer' context at this ultralow level. Certainly there would not be useful warranty ability on reliability of computation as the device was sold "as a VAX", and not a "general purpose CPU emulator".

Bill Wiese
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