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I was studying assembly and I came across the question about the double word in assembly. So, assuming i'm programming for x86-64 and use the instruction CALL DWORD PTR DS: [402068], but how it works, since a word in x86-64 is 64 bits, a double word would be 128 bits, In this particular instruction he takes the DS address and uses it as an argument to CALL, and the rest is not important (and I don't know either) but if it were a word it would be simple to change EIP and then jump, but taking a double word, I don't see how it would jump if the registers that handle memory for execution are 64 (EIP and PC), the only option would be get 128, but only use 64, is that right?

Loliconaoquadrado
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    x86 uses `dword` for 32 bits, no matter the mode. `word` is 16 bit, `qword` is 64. For historical and compatibility reasons. – Jester Sep 20 '20 at 00:05
  • Jester, thank you so much, No have reason to keep the same syntax as the x86-16 family, with the arrival of the x86-32 and x86-64 family, they just left it as it is out of laziness? – Loliconaoquadrado Sep 20 '20 at 00:11
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    All these machines retain the ability to run in 16-bit mode, in which they are essentially backward-compatible all the way to the 8086, and so 8086 assembly code should not change its behavior. I suppose Intel thought it would be too confusing if `WORD` had different meanings depending on the mode for which the assembler was generating code. Especially for things like bootloaders, which may mix 16-, 32- and 64-bit code in the same source file; what should `WORD` mean then? – Nate Eldredge Sep 20 '20 at 00:22
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    So I wouldn't call it "laziness". Indeed, if they'd really been lazy they wouldn't have bothered to provide backward compatibility at all. (Which might have been better in the long run...) – Nate Eldredge Sep 20 '20 at 00:23
  • There is actually good reason to keep the syntax the same: and instruction like `cwde` does exactly the same thing regardless of what mode you assemble and run it in. AX is always a "word" register. You need some name for 16-bit operand-size in 32 and 64-bit mode. See [What's the size of a QWORD on a 64-bit machine?](https://stackoverflow.com/q/55430725). Invaliding old documentation and making it confusing to port code to 32-bit mode would not have been helpful. – Peter Cordes Sep 20 '20 at 00:40
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    Nate Eldredge, intel did it in the 64-bit generation with titanium, it didn't work well either in the long run or in the short. – Loliconaoquadrado Sep 20 '20 at 00:41
  • What's your point about Itanium? IA-64 was a completely new ISA, basically unrelated to x86. AMD developed AMD64 aka x86-64 (which this question is about); Intel adopted it later. – Peter Cordes Sep 20 '20 at 00:42
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    Peter Cordes, I am saying that although the above comment refers to the fact that intel withdraws compatibility with previous versions of the x86 family, it would not be accepted by the market, like Itanium. – Loliconaoquadrado Sep 20 '20 at 00:48
  • @Loliconaoquadrado. IA-64 is not Intel's version of AMD64. EPIC originated at HP (PA-WideWord) and further developed by Intel/HP starting in 1996 resulting in the IA-64 ISA and the Merced FCS in 2001. By the way, Intel makes a number of chips that are not x86-compatable. StrongARM (ex DEC) was one such chip. – fpmurphy Sep 20 '20 at 04:08

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