How to use CommMonitor in gem5

Question

I want to record the access details of the cache. I saw some answers, saying that CommMonitor can help. But no more details were found.

How to trace the data that is going through caches and DRAM memory in gem5?

Obtaining physical address trace from GEM5

The above are some answers about CommMonitor. I have some questions about CommMonitor?

1. First of all, can Commmonitor be used for DerivO3CPU or only TimingSimpleCPU? I tried it on DerivO3CPU and there was output. But somewhere I seem to hear that it cannot be used for DerivO3CPU.

2. My understanding of CommMonitor is that it is like a filter. The data flowing through it is recorded. For example, add commMonitor between l2 and membus,

        system.monitor2 = CommMonitor()
        system.monitor2.trace = MemTraceProbe(trace_file = "CT_mon2.trc.gz")
        system.monitor2.slave = system.l2.mem_side
        system.membus.slave = system.monitor2.master
        system.l2.cpu_side = system.tol2bus.master
   

The output format is :

 11500: system.monitor2: Forwarded read request
  77000: system.monitor2: Latency: 65500
  77000: system.monitor2: Received read response
 103000: system.monitor2: Forwarded read request
 104000: system.monitor2: Forwarded read request
 165000: system.monitor2: Latency: 62000
 165000: system.monitor2: Received read response
 170000: system.monitor2: Latency: 66000
 170000: system.monitor2: Received read response
 194500: system.monitor2: Forwarded read request
 200500: system.monitor2: Forwarded read request
 243000: system.monitor2: Latency: 48500
 243000: system.monitor2: Received read response
 249000: system.monitor2: Latency: 48500
 249000: system.monitor2: Received read response
 267500: system.monitor2: Forwarded read request
 269500: system.monitor2: Forwarded read request
 274000: system.monitor2: Forwarded read request

The generated CT_mon2.trc.gz file is a binary file after decompression, what should I do to see the data inside? It would be better if I can output the address and data

3. How to use it between l1dcache and cpu?

Answer 1

3. How to use it between l1dcache and cpu?

Edit gem5/src/cpu/→ BaseCPU.py as following and don't forget to build after any changes you do to the src folder:

You can use flags(as follows) to see whats passes through this master-slave interface.

build/X86/gem5.opt --debug-flags=CommMonitor --debug-file=trace.txt.gz configs/learning_gem5/part2/simple_cache.py

Find trace.txt.gz in the m5out folder.