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I have Makefile like this:

obj-m += some_kernel_module.o
all:
    make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
    make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

It works when I run make from build machine locally (when my current directory is /home/myaccount/src/some_kernel_module/).

However when I'm trying to compile this remotely in Netbeans I'm getting this error:

/usr/src/linux-headers-3.16.0-6-common/scripts/Makefile.build:44: /home/myaccount/Makefile: No such file or directory

I guess that's because I have M=$(PWD) in my Makefile, and Netbeans Build Host current directory is my home (/home/myaccount) instead of project directory /home/myaccount/src/some_kernel_module/).

How can I fix that?

I have entered path manually and it works locally and remotely:

obj-m += some_kernel_module.o
all:
    make -C /lib/modules/$(shell uname -r)/build M=/home/myaccount/src/some_kernel_module/ modules
clean:
    make -C /lib/modules/$(shell uname -r)/build M=/home/myaccount/src/some_kernel_module/ clean

But this is not an answer. I don't want this absolute path in my Makefile.

Kamil
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1 Answers1

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I found answer here:

How to get current relative directory of your Makefile?

I had to get and store makefile directory like this:

THIS_DIR := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))

And use it instead of PWD (complete Makefile):

obj-m += some_kernel_module.o
THIS_DIR := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
all:
    $(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(THIS_DIR) modules
clean:
    $(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(THIS_DIR) clean

Edit: As https://stackoverflow.com/users/939557/madscientist suggested in comments below I changed make to $(MAKE).

Kamil
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  • You should always use `$(MAKE)` when invoking sub-makes, never `make`. – MadScientist Nov 27 '20 at 23:08
  • @MadScientist Looks like I have read wrong kernel driver tutorial... Thanks for suggestion. Is that because we don't want to run multiple processes or something like that? – Kamil Nov 27 '20 at 23:19
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    Is what? Using `$(MAKE)`? It's so that (a) if you run `gmake` (or whatever) instead of `make` that your sub-makes are also `gmake`, (b) all appropriate command line flags and variable overrides are passed to sub-makes, and (c) parallel builds are set up properly for sub-makes. – MadScientist Nov 28 '20 at 14:26