1

I have 2 thread bonded to 2 cpu core separately.

thread A and thread B have the same cache line data.

If I modified the cache line data and call _mm_clflush (void const* p) in thread A.

The cache line (L1,L2,L3) in thread B will become invalid and only can be read from main memory again.

Is that right ?

hi_glenn
  • 67
  • 1
  • 5
  • yes; the store in thread A will invalidate core B's copy of it, and clflush will invalidate all copies including in L3, so thread A has to re-read from RAM, not L3 or any kind of direct transfer between cores (on microarchitectures that can do that.) – Peter Cordes Dec 29 '20 at 13:21

1 Answers1

4

The answer is yes.

According to the Intel documentation, the CLFLUSH instruction invalidates the cache line in the entire "cache coherency domain". It is therefore not limited to the shared cache (normally Level 3 Cache), but also affects the dedicated cache of all other CPUs (i.e. their Level 1 and Level 2 Cache).

So, the next time a read takes place from that cache line, it will have to be read from main memory again.

Andreas Wenzel
  • 22,760
  • 4
  • 24
  • 39
  • 2
    x86 loads are strongly ordered; a speculative early load will cause a memory-order mis-speculation if the line is invalidated before the core is architecturally allowed to have read the line. (memory-order mis-speculation: [Why flush the pipeline for Memory Order Violation caused by other logical processors?](https://stackoverflow.com/q/55563077)). Putting any kind of barrier before a load would be pointless unless you're blocking local StoreLoad reordering wrt. earlier stores in that thread/core. (and HW prefetch is just into cache, where it's still coherent and can still be invalidated) – Peter Cordes Dec 29 '20 at 13:25
  • 2
    I have temporarily removed the disputed paragraph. I will look into it tomorrow. – Andreas Wenzel Dec 29 '20 at 21:41