I have understood how the cache coherence FSM works for single private L1 cache and a common LLC/memory. But couldn't find good resources where they discuss about cache coherence when there are 2 private caches - L1 and L2 and a common memory. I don't understand where the interconnection network is placed in the whole model, what does L1 caches snoop and their FSM.
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Peter Cordes
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Usually modern designs use directory-based coherency so you don't have a common snoopable bus as a bottleneck for all cores' traffic to LLC. Semi-related: [Which cache mapping technique is used in intel core i7 processor?](https://stackoverflow.com/q/49092541) mentions how Intel uses inclusive L3 tags as the directory. – Peter Cordes Jan 10 '21 at 05:08
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Does this answer your question? [Cache coherency(MESI protocol) between different levels of cache namely L1, L2 and L3](https://stackoverflow.com/questions/66731349/cache-coherencymesi-protocol-between-different-levels-of-cache-namely-l1-l2-a) – Peter Cordes Mar 11 '22 at 05:21