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I have received an error when i launched "make"

I didn't know where is the problem.

I guess in the makefile. Can you help me !Thanks :)

make: Circular src/amqp_consommateur.c <- obj/amqp_consommateur.o dependency dropped. make: Circular src/amqp_producteur.c <- obj/amqp_consommateur.o dependency dropped. make: Circular src/amqp_producteur.c <- obj/amqp_producteur.o dependency dropped. gcc obj/amqp_consommateur.o obj/amqp_producteur.o -o amqp_consommateur amqp_producteur -L. -lamqp gcc: error: obj/amqp_consommateur.o: No such file or directory gcc: error: obj/amqp_producteur.o: No such file or directory gcc: error: amqp_producteur: No such file or directory make: *** [src/amqp_producteur.c] Error 1

CC := gcc
CFLAGS := -Wall -Werror -g
SRCDIR := src
OBJDIR := obj
LDFLAGS :=
LIBS := -L. -lamqp
PROG := amqp_consommateur amqp_producteur
SRCS_RAW := amqp_consommateur.c amqp_producteur.c
#addprefix : src/amqp_consommateur obj/amqp_consommateur.o
SRCS := $(addprefix $(SRCDIR)/,$(SRCS_RAW))
OBJS := $(addprefix $(OBJDIR)/,$(SRCS_RAW:.c=.o))

.PHONY: all
all: $(OBJS)
    @echo "$(MAKE) : Tout est généré"

$(SRCS) : $(OBJS) 
    $(CC) $(OBJS) -o $(PROG) $(LIBS)
#rule to create object directory if it doesnt exist
$(OBJDIR):
    mkdir $(OBJDIR)
#define implicit rule to build objects in their own directory
#(note -- order only dependency on object directory)
$(OBJS): $(OBJDIR)/%.o: $(SRCDIR)/%.c | $(OBJDIR)
    $(CC) $(CFLAGS) -c $< 
.PHONY: clean
clean:
    $(RM) *~  $(EXEC)
    $(RM) -r $(OBJDIR)

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  • 1
    The first problem you get is "circular dependency". The is because you have rules `$(SRCS) : $(OBJS)` and `$(OBJS): $(OBJDIR)/%.o: $(SRCDIR)/%.c | $(OBJDIR)`. – Tsyvarev Jan 27 '21 at 09:01
  • @Tsyvarev: how can i resolve it ? – Embeded_developer Jan 27 '21 at 09:04
  • The command `$(CC) $(OBJS) -o $(PROG) $(LIBS)` generates `$(PROG)`, not `$(OBJS)`. So you need to adjust rule accordingly. – Tsyvarev Jan 27 '21 at 09:09
  • 1
    Does this answer your question? [Makefile to compile multiple C programs?](https://stackoverflow.com/questions/5950395/makefile-to-compile-multiple-c-programs) – Tsyvarev Jan 27 '21 at 09:09

1 Answers1

0
CC := gcc
CFLAGS := -Wall -Werror -g
LDFLAGS :=
LIBS := -L. -lamqp
SRCS := amqp_consommateur.c amqp_producteur.c

OBJS := $(SRCS:c=o)
PROGS := $(SRCS:.c=)

.PHONY: all
all: $(PROGS)
    @echo "$(MAKE) : Tout est généré"

$(PROGS) : % : %.o Makefile 
    $(CC) $< -o $@ 

%.o: %.c Makefile
    $(CC) $(CFLAGS) -c $< 

clean:
    rm -f $(PROGS) $(OBJS)