I'm writing a Terminal Match-Anything Pattern Rule, i.e.
%::
, that, as expected, will run only if no other target is matched. In its recipe I want to iterate over makefile's explicit targets and check if the found pattern ($*
) is the beginning of any other target
By now I'm successfully getting all desired targets in a space-separated string and storing it in a variable TARGETS
, however I couldn't turn it in an array to be able to iterate over each word in the string.
For instance
%:: $(eval TARGETS ::= $(shell grep -Ph "^[^\t].*::.*##" ./Makefile | cut -d : -f 1 | sort)) echo $(TARGETS)
gives me just what I was expecting:
build clean compile deploy execute init run serve
The Question
How could I iterate over each of $(TARGET)
string words inside a GNU Make 4.2.1
loop?
I found a bunch of BASH solutions, but none of them worked in my tests: