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In 8086 microprocessor:

MOV AL,5[SI][BP]

here's the effective address according to how i calculate: SS*10 + SI + BP + 5 as BP is offset register for stack segment.

But, SI is a offset register for data segment. So, I think base address of DS should contribute in some to the physical address But that not the case. Why? How is the Offset working here?

Isac
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  • BP as the base implies using the SS segment by default, not DS. That's why it's normally used for accessing stack memory. – Peter Cordes Feb 17 '21 at 12:58
  • (also [What segment is used by default in x86 indirect addressing?](https://stackoverflow.com/q/3948961) is an earlier duplicate with an answer that only discusses 16-bit). – Peter Cordes Feb 17 '21 at 13:00
  • re: your edit, now the question makes some sense. Remember that in 16-bit addressing, `[SI+BP]` and `[BP+SI]` are the same thing; there's only one encoding that has both registers ([Why don't x86 16-bit addressing modes have a scale factor, while the 32-bit version has it?](https://stackoverflow.com/q/55657904)). So unless you want your assembler to reject `5[SI][BP]` as not encodeable, the only option is to use the ModRM pattern that means BP+SI. If you want to distinguish base from index, BP can only be a base, SI can only be an index, in 16-bit addressing modes. – Peter Cordes Feb 18 '21 at 00:39
  • So the Offset is `BP+SI+5`, and the segment is SS (with SS_base = SS<<4 in real mode, or whatever else in unreal or protected mode). So the linear address is `ss_base + BP+SI+5`. With paging disabled (like in real mode), the linear address is physical. – Peter Cordes Feb 18 '21 at 00:41

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