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To the best of my knowledge, page tables would store virtual addresses, residency bit and their corresponding physical addresses. Given that the CPU caches, L1, L2, L3 etc cache data from main memory into the cache, during load and store operations, can these caches actually cache entire page tables? Personally, I do not think so, because the L1, L2, L3 cache data from main memory into the cache using addresses from the Memory Address Register and should not be able to cache implicit virtual addresses. Even if it does, how do we tell which entry in the cache is a main memory data block or a virtual address? I hope I am not confusing myself here.

I have checked stack overflow but haven't found an answer to this question

The perfectionist
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  • x86 and ARM use hierarchical page tables that use physical addresses. These can be (and often are) cached as ordinary memory. In addition, paging structure caches may be implemented which are effectively TLBs for intermediate page table node data (https://stackoverflow.com/q/26945448/2467198). For linear page tables (where the page table is mapped into a linear portion of the virtual address space), the virtual address would need to be translated (possible TLB miss) but the data can still be cached (just like any other read of ordinary memory). –  Mar 11 '21 at 18:46
  • Thank you so much. The question I have I guess is can an L1 CPU cache or L2 CPU cache , cache an entire page table ? – The perfectionist Mar 11 '21 at 20:07
  • If one excludes the OS portion (in a multiple address space design, each address space typically has the 'top'/'negative' half used by the OS), the page table for a small process might fit in L1 (4KiB pages and 8B PTEs give a 512x compression for page table to data). Typically cache replacement policies will (rightly) favor recently or frequently used memory locations, so PTEs and intermediate page table node entries would typically be evicted. –  Mar 11 '21 at 21:24
  • Can the page table then be stored in an L2 cache ? – The perfectionist Mar 11 '21 at 21:47
  • L2 is not restricted from storing any part of memory. –  Mar 11 '21 at 23:12
  • On most modern microarchitectures, hardware page-walk (after a TLB miss) fetches data (page directory / table entries) from main memory via L1d or at least L2 cache. (If it doesn't hit in an internal page-walker cache of the decoded translation for some level(s) of the radix tree aka page tables.) Physical address space is basically flat; an OS can put a page table anywhere, usually somewhere it also has a virtual mapping for so it can *modify* the page table. – Peter Cordes Mar 12 '21 at 09:31

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