I have written a C code. I want to test it using the makefile as the code mainly revolves working around on command line arguments and returning an exit code with printf()
writing the reason. return 0; //SUCCESS
and return 1; //FALIURE
I used this article as a reference guide for my intended purpose.
Here is the structure for an idea.
MAKE = gcc
FILENAME = topcgpas.c
TARGET = topcgpas
compile:
$(MAKE) $(FILENAME) -o $(TARGET)
run: compile
./$(TARGET) students.csv a.csv
testAll: compile test1 test2 test3 test4 test5 test6
@echo "All done"
test1:
@echo "TEST: Incorrect number of arguments"
./$(TARGET) 1 2 3
test2:
@echo "TEST: Incorrect input/output filename"
./$(TARGET) no.csv output.csv
make testAll
gives me
gcc topcgpas.c -o topcgpas
TEST: Incorrect number of arguments
./topcgpas 1 2 3
Usage ./topcgpas <sourcecsv> <outputcsv>
make: *** [makefile:16: test1] Error 1
However, to my understanding it should complete the execution for all tests.