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I learned about differences of CISC architectures and RISC architectures.

As far as I know, RISC architecture is load-store architecture. So it consists of 3-step.

  1. Load (memory -> register)
  2. operation (cpu with register)
  3. store (register -> memory)

I understand this process with five stages of datapath(instruction fetch, instruction decode, execution, memory access, write back)

But I don't understand that CISC architecture that is register-memory architecture operates directly on memory.

How CPUs are based on CISC architectures work directly on memory?

Changjin Koo
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    Isn't that a function of the specific instruction set and the related implementation, more than the architecture style itself? Many CISC cpus are a translator wrapper around a RISC core - AMD Athlon was the first I knew about that did this. Taking this view, it is likely that operations that involve memory writes are doing a fetch/process/write pipeline in the translator wrapper. – PaulProgrammer Apr 15 '21 at 03:04
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    They don't work *directly* on memory, they just decode memory-destination instructions to load / ALU / store internal operations. e.g. [Can num++ be atomic for 'int num'?](https://stackoverflow.com/q/39393850) describes this because it's relevant for that answer, not an ideal duplicate though. – Peter Cordes Apr 15 '21 at 03:09
  • Also related [In x64, using "pop \[RAX\]", where is the value temporarily stored?]([In x64, using "pop \[RAX\]", where is the value temporarily stored?](//stackoverflow.com/q/58001187)). All the answers I'm finding are about modern x86 specifically, because 1. it's one of the few CISCs that's still relevant 2. because few people other than me have been writing answers with that kind of CPU-architecture detail on Stack Overflow, about other architectures. https://retrocomputing.stackexchange.com/ might have some info about older microcoded machines like 8086 and 6502 that don't decode to uops – Peter Cordes Apr 15 '21 at 03:41
  • Thank you very much!! You guys say that CISC architecture processing is internally implemented Load/ ALU/ Store, right? – Changjin Koo Apr 15 '21 at 04:15

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