0

I created the following makefile:

#COMPILER
CC=gcc
CFLAGS=-I./include/ -L. -Wl,-rpath=. -Wall
CORFLAGS=-I./include/ -c -ansi -pedantic-errors -Wall -Wextra -g
COFLAGS=-I./include/ -Wall -Werror -fpic -c
CSOFLAGS=-shared
#vpath
vpath %.h ./include/
vpath %.c ./test/
vpath %.c ./source/
vpath %.o ./obj/
#PATH
SOURCE=./source/
OUT=-o ./obj/$@
TEST=./test/
OBJPATH=./obj/
#LISTS
CFILESWP=$(wildcard ./source/*.c)
TFILESWP=$(wildcard ./test/*.c)
CFILES=$(notdir $(CFILESWP))
TFILES=$(notdir $(TFILESWP))
TOFILES=$(TFILES:.c=.o)
OFILES=$(CFILES:.c=.o)
OFILESWP=$(addprefix ./obj/,$(OFILES))
NAMES=$(TOFILES:_test.o=)
HFILES=$(CFILES:.c=.h)
    
    
.PHONY: clean debug release all

debug: CSOFLAGS+=-g
debug: libds.so

release: CSOFLAGS+=-O2
release: libds.so

test: $(NAMES)
        
all: libds.so $(NAMES)

%: %_test.c libds.so
    $(CC) $(CFLAGS) -o $@ $< -lds -g
    
#SHARED LIBRARY
libds.so: $(OFILES)
    $(CC) $(CSOFLAGS) -o libds.so $(OFILES)
    
#OBJFILES
%.o: %.c %.h
    $(CC) $(COFLAGS) -o $@ $< -g

#CLEAN
clean:
    rm -f *.o $(OBJPATH)*.o
    rm -f $(NAMES) libds.so

My make file creates a shared library which called libds.so on make command and creates compiled executables on make test command.

it takes source files called TARGET.c from /source/ directory a.k.a stack.c, queue.c, cbuffer.c and compiles them togeher with their test files from /test/ directory aka stack_test.c, queue_test.c, TARGET_NAME_test.c.

All the .h files are located in the /include/ directory.

and there is also a /obj directory which should contains all the object files which created after running the makefile.

How can I make this makefile better? How can I move all .o files to /obj directory after each run of make? Is it possible to create each "project" without the need to compile ALL the targets?

I mean, can I write make, which will create the shared library, and then write create stack and it'll create only executable of stack which compiles /source/stack.c, test/stack_test, include/stack.h and all other associated .h files which appear to be inside the code of the source files.

Can I somehow force the makefile to run and compile only the projects that can be compiled and not to stop the "making", the compilation of the files just because several projets that have syntax errors inside of them or some other errors?

For example: If I have the following projects: stack.c, queue.c, cbuffer.c and cbuffer cannot be compiled because something is wrong with its code.

I want to be able to run make and make test and compile the other projects that can be compiled like stack and queue and just show me the compilation error of cbuffer but not to stop the make process.

Thanks.

NoobCoder
  • 513
  • 3
  • 18
  • why would you want to compile with errors? Anyway, you can [call makefiles from other makefiles](https://stackoverflow.com/questions/2206128/how-to-call-makefile-from-another-makefile). so maybe try compiling individualy using makefile and call these makefiles using a master makefile . – RC0993 Jun 09 '21 at 07:28
  • 1
    The easiest way would be to call `make -k` which ignores errors and keeps going as much as it can. – raspy Jun 09 '21 at 08:43
  • Regarding your projects (such as `stack` and `cbuffer`), how is Make supposed to know how to build those executables, if you don't tell it? And how can we advise you how to explain it to Make, if you don't tell us? (And do you really have a header file (`.h`) for each source file?) – Beta Jun 09 '21 at 11:56
  • Did you try to tell make which specific target to make, in example `make stack` or `make stack queue`? – the busybee Jun 09 '21 at 14:12

0 Answers0