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This is the code I have written

PUSH BP
MOV BP,SP

MOV AX,2
MOV [BP-8+AX*3],7

When I emulate this in emu8086 , I can see the following

enter image description here

You can see the address that should be calculated to 2 , but here it is calculated to 18h. I tried changing the value of AX , but still it remains to 18h. So after few trials , I understood that it completely ignores AX and is calculating 8 * 3 = 24 = 18h. This [BP-8+AX*3] is a valid instruction. Why is this weird thing happening ?

Zarif
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    No, `MOV [BP-8+AX*3]` is **not** a valid instruction,see https://stackoverflow.com/a/52740601/634919. You won't find it in the table of supported addressing modes in any x86 manual, especially not for 16 bit. It's not very clear what EMU8086 has decided to execute instead (it has a lot of bugs in general) but it's certainly not what you want. – Nate Eldredge Jun 23 '21 at 05:40
  • I have tried to see the output of x86-64 gcc in https://godbolt.org/ and I saw similar instruction – Zarif Jun 23 '21 at 05:42
  • @NateEldredge do you happen to know any alternative for the 16 bit version to do what I am trying to do – Zarif Jun 23 '21 at 05:43
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    x86-64 supports a lot more addressing modes than the 16-bit 8086 did, but even so there is none where you can use 3 as a scaling factor. It can only be 1, 2, 4 or 8. (If you don't use a base register you can get multiplication by 3 by doing `[disp+reg+reg*2]`, and some assemblers may let you write `[disp+reg*3]`, but there is no way to get scaling by 3 together with a base register.) – Nate Eldredge Jun 23 '21 at 05:45
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    You just have to write more instructions. For instance, `mov si, ax`, `add si, si`, `add si, ax`, `mov word ptr [bp-8+si], 7`. You also should use `word ptr` or `byte ptr` to indicate the operand size or you are at the mercy of whatever default your assembler chooses. x86-16 allows only `bp/bx` as the base register and only `si/di` as index registers. `ax` can't be used in an effective address at all. – Nate Eldredge Jun 23 '21 at 05:48
  • `[RBP - 8 + RAX*3]` wouldn't be valid in 64-bit mode either. The scaled-index (in 32 and 64-bit addressing modes) is a 2-bit shift count, so only *1, *2, *4, or *8. Some assemblers allow stuff like `lea eax, [rax * 9]` as short-hand for `lea eax, [rax + rax * 8]`, but the latter is the only way it can be encoded into machine code. [Referencing the contents of a memory location. (x86 addressing modes)](https://stackoverflow.com/q/34058101) – Peter Cordes Jun 23 '21 at 07:20

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