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I'm using Simics 6.0.83 (Public Release Preview) with target defined based on qsp-client-core.simics and trying to boot coreboot binary as legacy BIOS.

Configuration I'm trying:

# In order to run this, the QSP-x86 (2096), QSP-CPU (8112) and
# QSP-Clear-Linux (4094) packages should be installed.

decl {
! Script that runs the Quick Start Platform (QSP) with a client processor core.

 params from "%simics%/targets/qsp-x86/qsp-clear-linux.simics"
  default cpu_comp_class = "x86-coffee-lake"
  default num_cores = 4
  default enable_efi = FALSE
  default bios_image = "/home/debian/dasharo/coreboot/build/coreboot.rom"
}

run-command-file "%simics%/targets/qsp-x86/qsp-clear-linux.simics"

When trying to run-command-file from simics CLI I'm getting:

[board.mb.cpu0.core[0][0] unimpl] Warning: Cache flush without writeback (will not warn again for this CPU).                                                                                 
[board.mb.cpu0.core[0][0] info] CAR segment [0xfef00000: 0xfef40000] added to board.mb.cpu0.mem[0][0]                                                                                        
[board.mb.cpu0.core[0][0] info] 0xc91: Writing to unknown MSR. Signaling GP fault.
[board.mb.cpu0.core[0][0] info] Exception 13 while calling the double fault handler. Triple fault.                                                                                           
Breaking on triple fault. Break on triple fault is controlled by the break_on_triple_fault attribute.

How I can try coreboot in Simics?

Piotr Król
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3 Answers3

3

I am curious hence cloned, built and booted coreboot with coreinfo as payload based on https://doc.coreboot.org/tutorial/part1.html

Simics runs CoreInfo with CoreBoot

Maybe you can check out my defconfig as below

Coreboot defconfig

James
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    From the Simics side, I use the same script "qsp-client-core.simics", point to the coreboot rom and turned off efi, just like yours. – James Aug 20 '21 at 15:09
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    Please note this is QEMU target binary, which is way different from close to hardware target that I hoped to boot with Simics. We don't need Simics to run QEMU target of coreboot. – Piotr Król Sep 08 '21 at 22:25
  • A "real" BIOS needs much more than just the core. The Simics QSP model is an X58-ICH10 platform in practice, which is a real platform model. It is a bit old though, and in practice quite similar to a "generic PC". Pairing the QSP platform with new cores makes it possible to run interesting instruction sets, but low-level software would still need to target the actual platform. It is not entirely given that a qemu boot core runs on the Simics QSP -- they are different in some details. – jakobengblom2 Sep 09 '21 at 17:45
2

Sounds like you need to debug why CoreBoot is not working on the model. Suggest turning on time stamps for the logs (log-setup -time-stamp) to see if the MSR is related to the triple fault. Also try trace-exception around the time of the issue to see which exceptions are involved. If you have built the binary yourself, applying the debugger to it should be straightforward.

About logging: How do I get time stamps on Simics log messages?

Note that CoreBoot might need to support the processor core variant used. The MSR indicated, as an example, is not available on "coffee lake". But it could just be CoreBoot probing available features.

If you want a small bootloader to play with, check out the open-source SlimBootLoader, at https://slimbootloader.github.io/supported-hardware/qsp.html

jakobengblom2
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    Thanks to this suggestions I managed to debug coreboot build. The problem is [here](https://github.com/Dasharo/coreboot/blob/master/src/soc/intel/common/block/cpu/car/cache_as_ram.S#L525), coreboot tries to program IA32_L3_MASK_1 . Unfortunately Simics value for MSRs 0x0-0x176 have value "get failed". I wonder how SlimBootloader and edk2-platform manage that. – Piotr Król Jul 07 '21 at 20:00
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    I see valid values for MSRs 0-0x176 when I run "board.mb.cpu0.core[0][0].msrs", but I can confirm that you're right that IA32_L3_MASK_0-N (0xC90...) are missing from the output... Jakob, do you know why that is? – Jimmy Wu Sep 09 '21 at 14:35
  • In general, it is not a good idea by code to assume any particular MSRs are present without first checking CPUID if they are supported on a particular platform. That said, sometimes the processor core model can be missing MSRs that would be found on the corresponding hardware core. That might be the case here. – jakobengblom2 Sep 09 '21 at 17:43
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I have no idea why Coreboot touches 0xc91 (which is part of Intel Resource Director Technology (Intel RDT) and obviously has different purpose unrelated to cache-as-ram). However, try this:

  • check current processor

simics> pselect "board.mb.cpu0.core[0][0]

  • locate address space where MSRs are mapped:

simics> board.mb.cpu0.core[0][0]->cpu_msr_space board.mb.cpu0.cpu_msr[0][0]

  • lookup mappings:

simics> board.mb.cpu0.cpu_msr[0][0].map

  • found no mapping on 0xc91

  • since Simics has model development tooling - create simple device model that implements missing registers

  • map such device to MSR's space using:

board.mb.cpu0.cpu_msr[0][0].add-map

Alternatively, you can setup default target for MSR space - in such case, all missing accesses (both reads and writes) would hit it:

simics> @ always_zeroes = SIM_create_object("set-memory", "zeroes", [["value", 0]])

simics> @ conf.board.mb.cpu0.cpu_msr[0][0].default_target = [always_zeroes, 0, 0, None]

First line instantiates model of "set-memory" class which is simple device that always returns its value (in this example, value is set to zero) and ignores writes.

Second line sets default target of MSR's address space such that all missing accesses goes to always_zeroes device.

Please note, the latter option would not ensure cache-as-ram logic as on real hardware, but it will help you to pass further. Either way, functional processor model in Simics does not implement caches as in hardware.

cigien
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Kovalex
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