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I'm trying to understand context switching in OSs in general. I have a couple of questions that I could not find the answers to.

I would really appreciate any insight on these.

  • Do context switches happen mid instructions? If not, is it true for multi-step instructions (x86) like INC, XADD?
  • On which processor is the code responsible for context switching is run? If it is run on an arbitrary processor, that could modify the registers on that processor, right? So how does the OS manage to save that particular processor's state?
tecs-x
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Thanuja Dilhan
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    The first part of the question is a duplicate of https://stackoverflow.com/questions/55180452/interrupting-an-assembly-instruction-while-it-is-operating. For the second part, a kernel has to have code that handles each architecture for which is can be built. – Thomas Jager Jul 11 '21 at 16:18
  • Also, questions should generally be a single question, since, among other reasons, that enables marking as duplicate if that particular question already has an answer here. – Thomas Jager Jul 11 '21 at 16:24
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    The context switch runs on the processor that needs the context switched. Processors can't see each other's register state. – Jester Jul 11 '21 at 16:48
  • Yes in non-x86 yes but that is part of the architecture, either the instruction can be interrupted during execution (multi word store or load for example) and re-started after execution or it has to complete execution. It would by definition be a broken architecture if it allows for instructions to be interrupted before competing without any mechanism to recover. And it wouldnt be a very popular solution if every ISR had to do the recovery in software (for all the possible instructions that might have been interrupted), so this would need to be handled in the logic. – old_timer Jul 12 '21 at 11:30

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First of all, please do not restrict OS to Windows :D

Do context switches happen mid instructions? If not, is it true for multi-step instructions (x86) like INC, XADD?

In the software context switching, context switch will happen on a specific interrupt (A hardware timer, or an internal CPU tick counter timer). All of the CPU's architectures (AFAIK) have a register or flag to notify the "Fetch Unit" that there is a pending interrupt. Then, the CPU starts executing ISR by setting the PC register. Pay attention context switch will be done on an ISR. So, According to the interrupt mechanism, occurring an interrupt during executing an instruction, does not have any conflict. This way the current instruction will execute completely, But the "Fetch Unit" will load the first ISR instruction (After the hardware stack frame operation, in most of the architectures).

Although, some of the recent CPUs architecture have a Hardware Context Switching mechanism. In this way, All of the context switching processes will be done and handled by the CPU's hardware. To trigger a context switch and tell the CPU where to load its new state from, the far version of CALL and JMP instructions are used in the Intel CPUs architecture.

On which processor is the code responsible for context switching is run? If it is run on an arbitrary processor, that could modify the registers on that processor, right? So how does the OS manage to save that particular processor's state?

Each processor has its own context switch. In this way, Each processor has a particular scheduler in the kernel and OS (by observing the load balance on processors) will assign each task to one of the processors (at least in Linux).

HamidReza
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    Your hardware description is assuming a simple in-order CPU like 8086 or something. On real hardware that's likely to be running Linux, see [When an interrupt occurs, what happens to instructions in the pipeline?](https://stackoverflow.com/q/8902132) and [Interrupting an assembly instruction while it is operating](https://stackoverflow.com/q/55180452) - the CPU rolls back to the last consistent state. – Peter Cordes Jul 11 '21 at 20:16