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Is there a standard C++ equivalent for __memory_barrier, the "compiler fence" found in Intel's C++ compiler?

I'm under the impression that calling atomic_thread_fence with memory_order=memory_order_acq_rel should do the trick, is this the case?

Peter Cordes
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Lorah Attkins
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  • That's overkill; if anything you want `atomic_signal_fence(mo_seq_cst)`, although some of the equivalence may only be an implementation detail, but in practice that's how compilers do it. – Peter Cordes Aug 02 '21 at 11:01
  • How about `std::barrier`? – eerorika Aug 02 '21 at 11:01
  • @eerorika: https://en.cppreference.com/w/cpp/thread/barrier `std::barrier` is a *thread* barrier, that waits for n threads to reach it, then allows them all to continue. Basically nothing to do with memory barriers that order a single thread's access to coherent cache. – Peter Cordes Aug 02 '21 at 11:03
  • @PeterCordes so judging from your answer on the linked question, I should consider my assumption on `atomic_thread_fence` correct right? – Lorah Attkins Aug 02 '21 at 12:43
  • No, like I commented, the equivalent is atomic **signal** fence, since you only want to prevent compile-time reordering, not runtime reordering (on weakly-ordered ISAs where runtime reordering other than StoreLoad is possible). I double-checked and https://en.wikipedia.org/wiki/Memory_ordering#Compile-time_memory_barrier_implementation says that ICC's `__memory_barrier()` is just a compiler barrier. – Peter Cordes Aug 02 '21 at 13:07
  • Or do you mean combining the effect of a compiler barrier with the x86 memory model, since ICC can only target x86? (Rather than portably doing just a compiler barrier). Then yes, as far as inter-thread ordering, that is `atomic_thread_fence(mo_acq_rel)` - no asm instructions on x86, but takes instructions on weakly-ordered ISAs. – Peter Cordes Aug 02 '21 at 13:08

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