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I've got a question regarding an SMP system with multiple threads belonging to the same process:
Do all these threads share a single page-tree and the accessed and dirty bits of the PTEs in the tree are atomically (read-modify-write-operation) updated (accessed & dirty bit) according to the PTE-caches when they are flushed back?

Or are there up to the number of threads duplicate page-tables which are each dedicated to a single thread while it is running (and recycled if another thread is running) so that there's no need to (rmw-)lock the memory holding the PTE-entries while updating the accessed- and dirty-bits while flushing the PTE-caches?

Peter Cordes
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Bonita Montero
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1 Answers1

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Every thread of the same process has the same CR3 page table.

Updates to PTE A and D bits are atomic, presumably done by microcode as a sort of atomic-OR. (IIRC, most modern x86 CPUs handle setting the A or D bit as a microcode assist on the load or store instruction that needs to set a bit that wasn't already set in the TLB entry.)

How prompt is x86 at setting the page dirty bit? quotes Intel's and AMD's manuals on the subject of "Automatic Locking" like the LOCK prefix.

Atomic RMW on updates is relatively cheap compared to the OS having to maintain a copy of each process's page table for each HW thread, aka logical core (or for each software thread of a process if that was a smaller number). It's already a slowish microcode assist to have the CPU set a bit. Also, you don't want N copies of the page tables wasting L3 cache footprint.

Peter Cordes
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