c++ memory order (sequential consistent)

Question

I'm reading about atomic and memory orders and i'm really confused.

1. first of all i want to know if we use sequential consistent as memory order for our atomic operation no statements before and after that can be reordered and they are execute exactly in the source code order ?
   
2. what does it mean when we say all threads see the same order of operations and there is a global total order ? (it would be great if you could explain with an example)

Answer 1

(1) No, a seq_cst operation isn't formally a seq_cst barrier like atomic_thread_fence(memory_order_seq_cst). On some machines a seq_cst store does end up using a full barrier, though, in the asm. See https://preshing.com/20130922/acquire-and-release-fences/ re: acquire and release operations (allowing one-way reordering) vs. fences for acquire and release; a similar thing applies for seq_cst.

Even in practice seq_cst loads are weaker than full fences on many machines, not preventing some kinds of reodering across them.

On AArch64, seq_cst pure-load and also pure-store are done with special instructions that won't do StoreLoad reordering past each other, but wrt. plain store and load instructions they only have the semantics of acquire and release operations. (One-way reordering allowed: https://preshing.com/20120913/acquire-and-release-semantics/).

See also

• Does STLR(B) provide sequential consistency on ARM64?
• What exact rules in the C++ memory model prevent reordering before acquire operations?
• Why is acquire semantics only for reads, not writes? How can an LL/SC acquire CAS take a lock without the store reordering with the critical section?

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(2) guarantees no IRIW reordering. Will two atomic writes to different locations in different threads always be seen in the same order by other threads? has an answer that explains how POWER hardware can actually produce that reordering in practice (for mo_acq_rel or weaker).

This is one of those cases where the thing being guaranteed against is something you probably didn't imagine was something that needed worrying about in the first place. :P Most hardware (and most ISA on-paper specs) are multi-copy atomic, and do guarantee that there's always a single total order of stores that all observers can agree on. (But note that load data can come from store-fowarding: Globally Invisible load instructions)