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Background information

As a modern days PHP developer with a passing interest in 8-bit technologies, I'm a little sketchy on real low level stuff. Although I've worked with the Z80 processor, and done some MIPs assembly at University, I'm least well versed in the 65x processor family.

What I'm trying to achieve

What I want to do is to relocate the zero page to 0xd300 for my application - I've had a obligatory Internet search but am not able to find a good example that I am able to understand. I'm working in 65c02 but on a 65816 processor; I have found out, thanks to a friend, that you can only relocate the zero page in native mode, not emulation mode as it's not supported by the 65c02. This isn't an issue as I can switch to native mode for what I'm doing and revert to emulation mode should I want to return gracefully to BASIC (well, not only that I know).

If someone could also provide an example for the 8502 (Commodore C128) as well please as I know that has a relocatable zero page. I know that's two questions in one, but it's related to what I want to do.

Shaun Bebbers
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1 Answers1

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The Direct Page register D is a 16-bit register specifying which 256-byte page within bank 0 that should be the current Direct Page (what you call Zero Page).

There are a couple of different instructions you can use to write to D. So e.g. something like this should work:

rep #$20  ; 16-bit accumulator
lda #$100
tcd       ; transfer 16-bit accumulator to D

Note that the page is allowed to start on any byte boundary. So you could e.g. set D=2 and have a direct page at [0002, 0101].

Michael
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  • Excellent. This is very useful to know as the first 16-bits of the zero page on the Commodore C64 and C128 are taken by the processor ports and data direction registers. It might therefore be useful to set the D register to `0x0002` as you've suggested. – Shaun Bebbers Oct 20 '21 at 14:03
  • One caveat: if the Direct Page doesn't start on a page boundary (i.e., the the Direct Page Register isn't a multiple of 256) then all instructions using Direct Page addressing modes take an extra cycle to execute. (The CPU has special logic to detect when the low-order byte of the DPR is zero, in which case it simply ORs the direct page offset with the DPR, but if the low-order byte of DPR is non-zero it must do an add with carry, which takes an extra cycle.) – tim1724 Mar 11 '22 at 19:29