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Which logical processor belongs to the P-core group and which to E-core group?

My first idea was to just check the base clock for each logical processor and then assume that the lowest base clock belongs to E-core (according to intel specs E-cores always have a noticeable lower base clock than P-core).

I was hoping that checking HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor in the Registry would be enough. Unfortunately ~MHz always contains base clock of P-core.

Peter Cordes
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Atak_Snajpera
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    Suggest taking a look at [Game Dev Guide for Alder Lake Performance Hybrid Architecture](https://www.intel.com/content/www/us/en/developer/articles/guide/alder-lake-developer-guide.html) which includes non-Delphi code to get this information from some Windows APIs and the CPUID instruction. – Brian Nov 13 '21 at 16:25
  • Yes, this question is arguably incorrectly tagged. This is about Windows, hardware, CPUs. It's not about Delphi at all. – Andreas Rejbrand Nov 13 '21 at 18:04
  • [P=performance, E=efficiency](https://en.wikipedia.org/wiki/Alder_Lake_(microprocessor)#CPU) - it's no surprise the former is clocked higher than the latter. – AmigoJack Nov 13 '21 at 19:15
  • [How can I distinguish between high- and low-performance cores/threads in C++?](https://stackoverflow.com/q/68444429) is about the general case. But the answers there basically just say you normally don't need to. There is apparently some CPUID difference, that's what some game anti-piracy systems have a problem with. (But the BIOS can hide that, so IDK.) – Peter Cordes Nov 13 '21 at 19:27
  • You could run a microbenchmark that depends on AH being renamed separately from RAX on the P cores but not the E cores, or something like that. [How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent](https://stackoverflow.com/q/45660139) - Sandybridge-family still does partial reg renaming of high-8-bit registers, unless that was dropped for Ice Lake. So you could craft a loop that's much slower clock-for-clock on an E core by intentionally creating a false dependency for CPUs without partial-reg renaming. – Peter Cordes Nov 13 '21 at 19:29
  • Correction to previous comment, that BIOS workaround apparently is only based on disabling E-cores (temporarily via scroll-lock on some systems), not changing their CPUID results on them. So yeah, you can just run a CPUID instruction to find out what core you're currently on. Use thread affinity to get a thread migrated to each core in turn if you insist, although that wastes energy and time waking them all up. `/proc/cpuid` on Linux may have enough model/family info for each core so you can just read it. – Peter Cordes Nov 13 '21 at 21:46

1 Answers1

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The CPUID instruction gives information about the core, on which it is executed. It is different for P cores and E cores.

The CPUID on Alder Lake is family 6 model 0x9A for both cores when enabled. The CPUID is changed to family 6 model 0x97 when E cores are disabled and AVX512 is enabled.

CPUID leaf 7 EDX bit 15 indicates a hybrid design.

CPUID leaf 1A EAX bit 24-31 indicates the type of core, according to "Game Dev Guide for Alder Lake Performance Hybrid Architecture", https://www.intel.com/content/www/us/en/developer/articles/guide/alder-lake-developer-guide.html

See my discussion at https://www.agner.org/forum/viewtopic.php?f=1&t=79

janekb04
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A Fog
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