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When reading about cache coherence systems (e.g. MESI) I've not a clear understanding about the timing involved.

Consider the case in which a Core1 wants to write to a cache line in state MESI S on its local cache. The local cache controller has to initiate an RFO to invalidate that line on all other caches in the cache coherence domain.

I believe all cache transactions are actually based on a clock interval so in the clock interval in which the RFO takes place other Cores (e.g. Cores2) are not allowed to read that cache line from their local cache (even if before the RFO takes place that line was locally in S MESI state).

Can you help me in understanding how things works from a clock timing point of view ?

Peter Cordes
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Carlo C
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  • From [memory-barriers-force-cache-coherency](https://stackoverflow.com/questions/30958375/memory-barriers-force-cache-coherency) it seems the invalidation queue may allow the Core2 to read stale values from that cache line. – Carlo C Dec 01 '21 at 15:20
  • From this paper [Memory Barriers: a Hardware View for Software Hackers](http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf) I've a doubt about the sequence of events in section 3.3. To me bullet no.7 cannot happen before CPU 1 cache controller does not process the 'read & invalidate' message for cache line 'a' sent from CPU 0 (namely bullet no.8) – Carlo C Dec 02 '21 at 12:43

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