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From this link I have read that compilers can emit multiple instructions to store a single value which will cause intermediate variables be written to memory until all the instructions are executed. This could tearing in a multi threaded env.

I want to confirm, is it also possible to have such intermediate values even caused by a single instruction if address is not aligned? as explained in this link: https://qr.ae/pGzIKj which essentially explains how a single unaligned load/store could cause multiple bus transactions and cause tearing.

Dan
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    If a store is split across two cache lines, a share-request for one or both lines from another core could arrive between commits to L1d, since both halves might not (and on many CPUs *can't*) commit simultaneously in the same cycle. See [Atomicity on x86](https://stackoverflow.com/q/38447226) re: why a single narrow-enough aligned store can be atomic. – Peter Cordes Dec 20 '21 at 01:47
  • So load/store from an unaligned address (not talking about cache alignment, only talking about data alignment) doesn't really cause any issues unless the unalignment is related to cache lines? because all load/store happen in that cache line block sizes and not specific data type sizes? – Dan Dec 20 '21 at 01:53
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    Depends on the microarchitecture / vendor. Intel since P6 guarantees that accesses which don't cross a cache-line boundary are atomic for sizes of 1,2,4, or 8 bytes on P6 and later, so misaligned data is fine except for cache-line splits. AMD only guarantees within the access is fully contained in an 8-byte-aligned chunk. [Why is integer assignment on a naturally aligned variable atomic on x86?](https://stackoverflow.com/q/36624881) – Peter Cordes Dec 20 '21 at 02:13
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    You can see it happen here: https://godbolt.org/z/f8Tr6hnKs (And then change 62 to 58 and watch it not happen anymore.) – Nate Eldredge Dec 20 '21 at 02:56
  • Thank you, so what is the information provided here about: https://qr.ae/pGzIKj ? does this not happen anymore on x86? or is this more like a theoretical explanation in a bigger picture. Could tear happen due to this behaviour also? – Dan Dec 20 '21 at 03:04
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    The discussion in that link is less specific, but I think it's talking about the same thing. An unaligned access may in principle cause two bus or cache accesses underneath, which can lead to tearing. For modern Intel x86 in particular, this only happens when the unaligned access actually crosses a cache line, but the test case above shows that it absolutely happens in that situation. – Nate Eldredge Dec 20 '21 at 03:15

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