SPI communication failed, nothing works

Question

I am trying a lot of days to acomplish a communication via spi (stm32-nrf24..) and it doesn't work despite that I had read a lot of resources I cant make it right and I dont know why this is happening, I realy need help. I have nucleol053r8 and nrf24l01 and I want to accive a communication between them. When I am truing to debug the spi, for example to write something on DR and after to read it, nothing works! It seems that nothing is writing to DR. My configurations for this communication are

1. CPOL=CPHA=0
2. FULL DUPLEX MODE
3. MSB FIRST
4. MASTER MODE ON
5. 8bit DATA FRAME
6. SSM=SSI=1

Here is my functions for reading and writing.

void spi1_transmit(uint8_t *data,uint32_t size){

uint32_t i=0;
uint8_t temp;

while (i<size){
    while (!READ_BIT(SPI1->SR,SPI_SR_TXE));
    SPI1->DR=data[i];
    i++;
}
while (!READ_BIT(SPI1->SR,SPI_SR_TXE));
while (READ_BIT(SPI1->SR,SPI_SR_BSY));
temp = SPI1->DR;
temp = SPI1->SR;

} void spi1_receive(uint8_t *data,uint32_t size){

while (size){
    SPI1->DR=0;
    while (!READ_BIT(SPI1->SR,SPI_SR_RXNE));
    *data++=(SPI1->DR);
    size--;
}

}

void spi1_gpio_init(){

/*Enable clock access to GPIOA*/
SET_BIT(RCC->IOPENR,IOPAEN);

/*Setting as AF functions the proper pins. */
CLEAR_BIT(GPIOA->MODER,(1U<<10)); // PA5
SET_BIT(GPIOA->MODER,(1U<<11));
CLEAR_BIT(GPIOA->OTYPER,(1U<<5));
SET_BIT(GPIOA->OSPEEDR,(1U<<10));
SET_BIT(GPIOA->OSPEEDR,(1U<<11));
// Setting AF type AF0.
CLEAR_BIT(GPIOA->AFR[0],(1U<<20));
CLEAR_BIT(GPIOA->AFR[0],(1U<<21));
CLEAR_BIT(GPIOA->AFR[0],(1U<<22));
CLEAR_BIT(GPIOA->AFR[0],(1U<<23));

CLEAR_BIT(GPIOA->MODER,(1U<<12)); //PA6
SET_BIT(GPIOA->MODER,(1U<<13));
CLEAR_BIT(GPIOA->OTYPER,(1U<<6));
SET_BIT(GPIOA->OSPEEDR,(1U<<12));
SET_BIT(GPIOA->OSPEEDR,(1U<<13));
// Setting AF type AF0.
CLEAR_BIT(GPIOA->AFR[0],(1U<<24));
CLEAR_BIT(GPIOA->AFR[0],(1U<<25));
CLEAR_BIT(GPIOA->AFR[0],(1U<<26));
CLEAR_BIT(GPIOA->AFR[0],(1U<<27));

CLEAR_BIT(GPIOA->MODER,(1U<<14)); //PA7
SET_BIT(GPIOA->MODER,(1U<<15));
CLEAR_BIT(GPIOA->OTYPER,(1U<<7));
SET_BIT(GPIOA->OSPEEDR,(1U<<14));
SET_BIT(GPIOA->OSPEEDR,(1U<<15));
// Setting AF type AF0.
CLEAR_BIT(GPIOA->AFR[0],(1U<<28));
CLEAR_BIT(GPIOA->AFR[0],(1U<<29));
CLEAR_BIT(GPIOA->AFR[0],(1U<<30));
CLEAR_BIT(GPIOA->AFR[0],(1U<<31));

SET_BIT(GPIOA->MODER,(1U<<18)); //PA9
CLEAR_BIT(GPIOA->MODER,(1U<<19));
CLEAR_BIT(GPIOA->OTYPER,(1U<<9));
SET_BIT(GPIOA->OSPEEDR,(1U<<18));
SET_BIT(GPIOA->OSPEEDR,(1U<<19));

SET_BIT(GPIOA->MODER,(1U<<16)); //PA8
CLEAR_BIT(GPIOA->MODER,(1U<<17));
CLEAR_BIT(GPIOA->OTYPER,(1U<<8));
SET_BIT(GPIOA->OSPEEDR,(1U<<16));
SET_BIT(GPIOA->OSPEEDR,(1U<<17));

} void spi1_config(){

/*Enable clock access to SPI1.*/
SET_BIT(RCC->APB2ENR,SPI1_EN);

/*Setting up BAUDRATE. FPCLK/32 (100) */
SET_BIT(SPI1->CR1,(1U<<5));   // 1.
CLEAR_BIT(SPI1->CR1,(1U<<4)); // 0.
CLEAR_BIT(SPI1->CR1,(1U<<3)); // 0.

/*Setting up CPOL=0 and CPHA=0.*/
CLEAR_BIT(SPI1->CR1,(1U<<0)); // CPHA=0.
CLEAR_BIT(SPI1->CR1,(1U<<1)); // CPOL=0.

/*Enable full-duplex mode.*/
CLEAR_BIT(SPI1->CR1,(1U<<10));

/*Set MSB first.*/
CLEAR_BIT(SPI1->CR1,(1U<<7));

/*Enable Master mode.*/
SET_BIT(SPI1->CR1,(1U<<2));

/*Setting up 8-bit data frame.*/
CLEAR_BIT(SPI1->CR1,(1U<<11));

/*Enable software slave management. SSM=1 and SSI=1.*/
SET_BIT(SPI1->CR1,(1U<<9)); // SSM=1.
SET_BIT(SPI1->CR1,(1U<<8)); // SSI=1.
cs_disable();
ce_disable();

/*Enable SPI peripheral.*/
SET_BIT(SPI1->CR1,(1U<<6));

}

and with this why am testing it

int main(void){

uint8_t tx_b[3],rx_b[3];
init_rcc();
spi1_gpio_init();
spi1_config();

tx_b[0]=0b00111111;
tx_b[1]=0b00001000;
tx_b[2]=0b00101000;
spi1_transmit(tx_b,3);
while(1){
    spi1_receive(rx_b,3);
}

}

Answer 1

1. You need to enable SPI clock
2. You need to enable the peripheral
3. Many STM32 SPIs have FIFO and you need to force the compiler to generate the correct size store instructions.

For example

*(volatile uint8_t *)&SPI1->DR = data[i];