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Hi I'm having trouble with understanding cache line and memory correspondence.

According to here,

"If cache lines are 64 bytes wide, then they correspond to blocks of memory which start on addresses that are divisible by 64."

Is this true?

If it is true, where I can find official document or such that explains it?

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In case of cache line size, I found it from Intel® 64 and IA-32 Architectures Optimization Reference Manual.

Peter Cordes
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YoonSeok OH
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  • CPU cache lines are *always* naturally-aligned so the address bits divide up into "offset-within-line" for the low bits, and "index" and "tag" portions for the higher bits, so yes, that's just a basic fact, so universal that Intel didn't feel the need to document it in their optimization manual. It might be mentioned somewhere, or at least implied by the wording chosen to describe some other point, IDK. Perhaps mentioned in [What Every Programmer Should Know About Memory?](https://stackoverflow.com/q/8126311) – Peter Cordes Feb 07 '22 at 10:54
  • https://en.wikipedia.org/wiki/Cache_placement_policies also has some illustrations – Erik Eidt Feb 07 '22 at 16:42

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