0

How do multi-processor atomic operations work? Suppose two Processors signal they want to access the same memory location at the same time - who gets control? Is it decided by internal circuitry?

FourierFlux
  • 439
  • 5
  • 13
  • 1
    For x86, see [Can num++ be atomic for 'int num'?](https://stackoverflow.com/q/39393850). For other ISAs, some use LL/SC (https://en.wikipedia.org/wiki/Load-link/store-conditional). For write-only atomic operations (not RMW), see [Can multiple CPUs simultaneously write to the same RAM location?](https://stackoverflow.com/q/516940) - yes, whichever core gets exclusive ownership of the cache line commits its store first. – Peter Cordes Feb 10 '22 at 23:25
  • So how does one verify they have attained control of a memory location if there isn't a set order for claiming access? Imagine 4 CPU all attempting to claim access to the same location at the same time - how does a core verify it has attained control? – FourierFlux Feb 10 '22 at 23:33
  • https://en.wikipedia.org/wiki/MESI_protocol - only one core will get a reply to its Read For Ownership granting it exclusive ownership, or acknowledgements from other cores that they've invalidated their copies. Intel engineers have said Intel CPUs have a "contention manager" that decides which cores should get access next if many are contending for access. – Peter Cordes Feb 10 '22 at 23:38
  • I forget if [What Every Programmer Should Know About Memory?](https://stackoverflow.com/q/8126311) mentions multi-core says anything about MESI and multiple cores. It's fairly old, when multi-core was very new (but still highly relevant). – Peter Cordes Feb 11 '22 at 00:26
  • And BTW, in my first comment, I linked [Can multiple CPUs simultaneously write to the same RAM location?](https://stackoverflow.com/q/516940) without really reading the answers. I retract my recommendation to see that Q&A. The top answer has a couple mistakes and doesn't say anything really specific. – Peter Cordes Feb 11 '22 at 00:27
  • See [What happens when different CPU cores write to the same RAM address without synchronization?](https://stackoverflow.com/q/48817022) for pure stores, and atomic ops on x86-style CPUs (single-instruction RMW, not LL/SC) – Peter Cordes Feb 11 '22 at 00:52

0 Answers0