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    asm volatile("cld\n\trepne\n\tinsl"
         : "=D" (addr), "=c" (cnt)
         : "d" (port), "0" (addr), "1" (cnt)
         : "memory", "cc");

Here insl is used so it is saying do input four times but wht tells it that when doing input four times instead of putting each byte at next memory address load it at one address only, but first byte at 0-7 than 8-15 than 16-23 than 24-31

Or you can say my problem are these lines except :

: "memory", "cc");

And in detail explanation of cld clear direction flag and effect on di and si plz with an example

OSdev
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    The `"1" (cnt)` matching constraint to put the C variable `cnt` into ECX on input gets the compiler to set ECX, which `rep insl` uses as the repeat count. It would be simpler to just use `"+c"(cnt)` instead of separate output and matching-input constraints. Same for `"+D" (addr)` to set EDI (or RDI if this is 64-bit mode). – Peter Cordes Feb 23 '22 at 08:22
  • `insl` is `ins` with an AT&T `l` suffix, meaning 32-bit dword, i.e. Intel syntax `insd`. https://www.felixcloutier.com/x86/ins:insb:insw:insd That's why it's doing dwords instead of bytes. IDK where you're getting 0-7 and 8-15, there is no `insq` form even in 64-bit mode. And you definitely can't scatter bytes with gaps between them, only contiguous bytes, words, or dwords. – Peter Cordes Feb 23 '22 at 08:23
  • The `"memory"` clobber is because your asm statement takes a pointer in a register as an input operand, and the pointed-to memory is not directly mentioned as an output operand. [How can I indicate that the memory \*pointed\* to by an inline ASM argument may be used?](https://stackoverflow.com/q/56432259). – Peter Cordes Feb 23 '22 at 08:28
  • The `"cc"` clobber is redundant: x86 inline asm implicitly has a `"cc"` clobber. Also, I don't think GCC ever sets DF=1 itself (and assumes DF=0 in its own code-gen), so the `cld` instruction is redundant. And there's no other change to EFLAGS made by code in the asm template, so EFLAGS isn't actually clobbered. – Peter Cordes Feb 23 '22 at 08:29
  • but 'Peter Cordes' during i/o instruction it loads only one byte so i was thinking insl was actually loading a byte from data register of controller first in lower location 0-7 than till 24-31 for four times. i think you are understanding wht i am saying can you solve is it loading four byte one after one in one memory location from controllers data register – OSdev Feb 23 '22 at 08:33
  • `insl` does one 4-byte IO-read operation, not 1-byte. `rep insl` with ECX=4 does four 4-byte IO-read operations from the same port. ATA PIO is slow, but at least HDD controllers could use the full 32-bit bus width. Or at least 16-bit? https://wiki.osdev.org/ATA_PIO_Mode#x86_Code_Examples shows an example using `rep insw` to read data in 16-bit chunks. The status register reads are normally 1-byte, but that's just a single read, not what you'd use `rep insl` for. I have no idea what you're saying with 0-7 and so on. That makes no sense. Are you talking about bits not bytes? – Peter Cordes Feb 23 '22 at 08:40
  • i was talking about bits but thanks a lot you solved my question, my problem was with port register as i thought i can only read 1 byte at a time as with data and control register of mouse controller and keyboard controller. – OSdev Feb 23 '22 at 08:49
  • sorry for inconvience while asking i forgot that every memory cell at particular location have only one byte so i wrote 0-7 8-15 and so on – OSdev Feb 23 '22 at 09:04

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