What does ‘$@’ mean when it isn't in a rule of a Makefile?

Question

# Linker scripts preprocessor (.lds.S -> .lds)
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds_S = LDS     $@
      cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \
                         -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<

$(obj)/%.lds: $(src)/%.lds.S FORCE
    $(call if_changed_dep,cpp_lds_S)

Above is the code in scripts/Makfile.build.I was reading the arch/arm/kernel/vmlinux.lds.S and I couldn't find the 'INPUT' for the linker script.I guessed the 'INPUT' is setted when the vmlinux.lds.S is compiled.Then I found the code above.I've learned that '$@' is the file name of the target of a rule.But this one is not in a rule.So what it represents and where is the 'INPUT'?

The short answer is that it expands to nothing outside of a recipe, _BUT_ variables (assigned with `=`) are not expanded when they are assigned, they are expanded when they are used. So, when this variable is expanded in a recipe and so the `$@` will expand to the name of the target just as if you'd typed `$@` in the recipe directly. — MadScientist, Mar 24 '22 at 13:16

score 0 · Accepted Answer · answered Mar 24 '22 at 06:56

You don't show it, but it is almost certainly the case that if_changed_dep is another macro defined elsewhere in that makefile that expands to either $(quiet_cmd_$1) or $(cmd_$1) (probably depending on how make was invoked, or what arguments it was given), so as applied ends up generating one of those two macro definitions as the action for the rule.

What does ‘$@’ mean when it isn't in a rule of a Makefile?

1 Answers1