This line appears under memory events in perf tool. CPU: Intel Xeon Gold
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"Precise" events mean using PEBS instead of the traditional firing an interrupt when the counter overflows. Instead it writes a sample in a buffer to be collected later, so it can attribute it to the right instruction without pipeline / retirement effects delaying it (e.g. waiting until the currently-last instruction retires, I think to ensure forward progress, causing a "skid").
The PEBS buffer also gives it a place to put additional data, like an address associated with the event that triggered recording a sample.
Also related with discussion about or details of PEBS and how perf uses it for event:pp -
Peter Cordes
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