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I want to find the expexted hazards in below code until clock cycle 7 with appropriate reasons and solution.

1: sub $2,$2,$3
2: lw $4, 0($2)
3: and $1,$4,$2
4: beq $1,$2,1
5: or $5,$1,$6
6: add $2,$5,$3

In my opinion


line2: Ex hazard (solution is forwarding)
line3: Ex hazard , mem hazard (solution is forwarding and add one bubble)
line5: Condition hazard 
line6: Ex hazard (forwarding)

I want solve this problem...

Erik Eidt
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newwwby
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  • Is this a fake MIPS without branch-delay slots? If so, say so in your question. I'm only guessing MIPS at all based on the syntax, and [a classic 5-stage RISC](https://en.wikipedia.org/wiki/Classic_RISC_pipeline) also seems likely but you didn't say. Real MIPS has a branch-delay slot, fully hiding branch latency ([thanks to clever HW design to keep that latency down to 1 cycle](https://stackoverflow.com/questions/56586551/how-does-mips-i-handle-branching-on-the-previous-alu-instruction-without-stallin)) so there's no bubble for ALU / branch / ALU instruction sequences; forwarding works. – Peter Cordes Apr 24 '22 at 03:06

1 Answers1

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You are mostly correct.

Let's further discuss that: instruction #3 has two hazards, both $4 and $2 are RAW dependencies of prior instructions.  Though the insertion of the bubble to cover the MEM-to-EX hazard delays instruction #3, it will still read a stale value for $2 so that other delay doesn't help: it will need a forward for that register as well.

You've missed the EX hazard with $1 on instruction #4.

Instruction #5 also has a RAW hazard on $1, and this will require forwarding, because instruction #5's ID stage (assuming branch not taken) overlaps with instruction #3's MEM stage, which is not sufficient to avoid the hazard of stale values in RAW dependencies.

Erik Eidt
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