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So what I know is that each virtual address space on x86_64 can be accessed with 48/57 addressing. So in 48 bit addressing you access low 47 bits (128TB) with 0-0x7FFFFFFFFFFF and the high 47 bits with 0xFFFF800000000000-0xFFFFFFFFFFFFFFFF so how about 57 bit addressing ? Does the processor automatically calculate that with lea (Load effective address) or the O.S has to do that manually (especially when putting kernel mode space on this high 128TB address space). Is what I'm thinking of right ?

git_lk1
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  • There is a discussion that may address your question. You have to look at all answers to find the good ones, many are misleading, but [this is one of the good ones](https://stackoverflow.com/a/6716976/645128) – ryyker Jul 25 '22 at 13:42

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The CPU requires that addresses are already correctly sign-extended to 64-bit (aka "canonical"), from 48 or 57-bit depending on whether 5-level paging is enabled in a control register.

This check happens when they're actually used to access memory. lea doesn't do that, it's just a shift-and-add instruction on the "offset" part of an addressing mode. lea has no interaction with canonical address requirements, and thus is safe for Using LEA on values that aren't addresses / pointers?

The check also happens in branch/call/ret/etc. instructions, before they update RIP. If an instruction tries to set a non-canonical RIP, you get a #GP(0) exception on that instruction. By contrast, jumping to an unmapped page succeeds, but then you get a #PF page fault with the new address. (This makes sense; it might not be an invalid page fault, the OS might just need to page in some code or just wire up the page table if the data's already somewhere.) Detecting a non-canonical address doesn't require a TLB check, either.

If PML5 is enabled, the check only applies to the high 64-57 = 7 bits of virtual addresses matching the 57th bit (bit #56). New CPUs support it, but it doesn't make sense for an OS to enable unless your system actually needs that much virtual address space. (Usually because you have boatloads of RAM.) The extra level of page tables slows down each TLB miss, and is more for the OS to manage.

Unless you use the upcoming AMD UAI (Upper Address Ignore) feature that make the CPU ignore high bits, or the recent Intel LAM (Linear Address Masking) hardware feature that makes the CPU only check the top bit against the most-significant (#47 or #56), not the bits in between.

These features allow tagged pointers without manually redoing sign or zero extension. (User-space can use zero-extension on normal OSes, because they know the kernel won't have given them addresses in the high half.)

See Using the extra 16 bits in 64-bit pointers for details of doing that without LAM / UAI. (Or high 7 bits on a system with PML5 enabled.)

Peter Cordes
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