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We know that every instruction is converted base + offset and the offset max size is set to 4K (4096). What if my program size is more than 4k?

Line 1 : Base  + 1 , 
Line 2 : Base  + 5 , 
.
.
.
., 
Line x : base + 4090

How the Line x onwards is addressed like Base + offset as the instruction is beyond the page size 4096?

How the instruction from Line X onwards is assembled? Do we need to change the base address to the starting of next page where the instruction is held?

Hogstrom
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Jijo
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  • Are you using x86-16bit or something else? (Please add the corresponding tag) – chtz Aug 07 '22 at 13:43
  • What architecture are you programming for? – fuz Aug 07 '22 at 14:07
  • On x86_32 and x86_64 instructions have nothing to do with page size. They operate with whole virtual address which later is translated by MMU to physical pages transparently for instructions. – dimich Aug 07 '22 at 14:12
  • Zos (Mainframe Z series) – Jijo Aug 07 '22 at 14:22
  • 32 bit addressing – Jijo Aug 07 '22 at 14:23
  • @Jijo Do you mean 31 bit addressing? – fuz Aug 07 '22 at 14:39
  • yes , 31 bit @fuz – Jijo Aug 07 '22 at 15:13
  • @Jijo So to answer the question, usually if the offset doesn't fit, you'll have to load the offset into a register and then use a register + register addressing mode. However, I don't know enough about S/390 to say for sure. – fuz Aug 07 '22 at 15:15
  • Actually, 24bit, 31bit, and 64bit are the three addressing modes offered by the IBM mainframe processors. They are not related to the question about base register and offset. – phunsoft Aug 07 '22 at 19:40
  • The short answer is that you simply need 2 base registers. (you need 1 register per 4K of addressable code). To avoid this, you can break your code into small (less than 4K) chunks or use relative addressing, There's a detailed answer covering these points. – Steve Ives Aug 12 '22 at 08:26

1 Answers1

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Addressing with IBM mainframe processors

The ancestor of today z/Architecture (IBM mainframe) processors indeed were only offering the base-offset addressing. You had to load a base address into a register, and then specified this base register plus a 12-bit offset, i.e. 0 to 4095 bytes to address some storage.

Addressing with S390/Architecture processors

The assembler offers the USING instruction to help you with this. You specify a label in your program and a register, that will hold the address of that labeled instruction at runtime. The assembler will then calculate the offset for you.

Example

         ...
         LA    R5,SUB01
         BALR  R4,R5
         ...
SUB01    DS 0H
         USING SUB01,R5
         ...
         B     SUB01A
         ...
SUB01A   DS    0H

Explanation: Some way down your program you need to call subroutine SUB01. You load its address into register 5 (R5), then branch while saving the return address into register 4 (R4). This is what the instructions LA R5,SUB01 and BALR R4,R5 do.

In your subroutine, you tell the assembler that R5 is pointing to the address SUB01 with the USING SUB01,R5. The assembler uses this information to build the branch instruction B SUB01A. It calculates the offset from SUB01 to SUB01A.

If the code starting at SUB01 is longer than 4096 bytes, the maximum offset, you need a second, third, fourth, etc register, which point to the next 4k segment, each.

Assuming the code is 10k long, you need three registers. The code might look like this:

         ...
         LA    R5,SUB01
         BALR  R4,R5
         ...
SUB01    DS 0H
         LA    R6,4095(,R5)    
         LA    R6,1(,R6)
         LA    R7,4095(,R6)    
         LA    R7,1(,R7)
         USING SUB01,R5,R6,R7
         ...
         B     SUB01A
         ...
SUB01A   DS    0H

Explanation: Upon entry to SUB01 you know that R5 point to that label. You need to load R6 with R5 + 4096, and R7 with R5 + 8192. There are different ways to achieve this. I'm showing the one using the load address LA instruction, which has a maximum offset of 4095 (architecture restriction).

The you tell the assembler that registers R5, R6, and R7 can be used to calculate the offsets. It will use R5 if the offset is 0-4095, R6 if the offset is 4096-8191, and R7 of the offset is 8192-12287.

Addressing with z/Architecture processors

With z/Architecture, IBM introduced a set of new instructions that use a 20-bit signed displacement. Those instructions use a signed offset, i.e they can address storage after the address in the base register, but also storage before that address. A 20-bit signed offset provides for relative addressing of up to 524,287 bytes beyond the base address location or of up to 524,288 bytes before it.

You can address much larger areas with those instruction using a single base register.

IBM z/Architecture Description

IBM documents its z/Architecture in a manual called z/Architecture Principles of Operation

Michael Petch
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