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So this is a question about computer organization Consider following instruciotns:

add $t2, $t2, $t2
nop
nop
add $t2, $t2, $t2

We can draw cycle diagram like:

add| IF| ID|EXE|MEM| WB|
nop|   |   |   |   |   |
nop|   |   |   |   |   |
add|   |   |   | IF| ID|EXE|MEM| WB|

first add is in WB stage and second add is in ID stage.

Textbook tell me that this won't make hazard since you can write Registerfile in first half cycle and read it in second half cycle. It doesn't make sence if we assume pipeline stage and registerfile both are positive edge trigger. The behavior can described by verilog like:

always @(posedge clk)begin
    if(RegWrite) regfile[waddr] <= wdata;
end

Here is the timing diagram I think: This

As you see when second add is reading registerfile, the new data is just being written. How can you write in first half cycle when RegWrite is "LOW"?

At least there will be a clk to Q delay. It is impossible to write register at positive edge.

If clock phase of pipeline register and registerfile are different, it's not a problem anymore, but no one said that. Or just simply tell me you can read data just being written somehow.

==============================

clk      __/‾‾‾\___/‾‾‾\___
RegWrite ____/‾‾‾‾‾‾‾‾\____

there must be a clk to q delay for RegWrtie. how Regfile write data at "clock edge" when RegWrite is LOW?

Mr.Knife
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  • What do you mean by this: How can you write in first half cycle when RegWrite is "LOW"? – Erik Eidt Sep 23 '22 at 12:25
  • "As you see when second add is reading registerfile, the new data is just being written." Yes, the data to write for WB is available at very the beginning of that cycle. The data to read is not required until the end of that same cycle -- it is then captured in the ID/EX pipeline register (at the end of that cycle). There is sufficient time (that whole cycle) for the register read in ID to obtain the value written by WB in that same cycle. – Erik Eidt Sep 23 '22 at 12:33
  • @ErikEidt you didnt get my point. RegisterFIle is postive edge trigger and write data only when RegWrite is "HIGH". This RegWrite is decode from ID stage and pass to WB stage. When posedge, RegWrite pass from EXE/MEM to MEM/WB stage, and there must be a "clk to Q delay" so at the same time Register CAN NOT write data. This is what I confuse. – Mr.Knife Sep 23 '22 at 15:20
  • "the data to write for WB is available at very the beginning of that cycle" Sure you are right, but it actually being ready after clk positive edge. – Mr.Knife Sep 23 '22 at 15:27
  • All the control signals are generated in ID and passed to the stage that needs them. RegWrite is 1/high when that first `add` instruction is in WB. – Erik Eidt Sep 23 '22 at 15:28
  • The WriteData/32, WriteReg/5, and RegWrite/1 are all stored in the MEM/WB pipeline register, and immediately available at the beginning of that WB cycle. The ID stage, in parallel is reading the register file, continuously until the end of the cycle. If it reads a register that is written in the same cycle, it's outputs will fluctuate, but eventually, by the end of that cycle, settle on the value written by WB. – Erik Eidt Sep 23 '22 at 15:30
  • @ErikEidt "at the beginning" of cycle literally means "after positive edge", however the register is positive edge trigger. So you try to tell me, register can write data "during a cycle" somehow just because RegWrite is high? – Mr.Knife Sep 23 '22 at 15:43
  • The WB write happens at the beginning of the WB cycle, probably taking less than hold time. All the necessary values/signals are there for it to use immediately upon the clock transition that starts that cycle. Why do you think that RegWrite is low at that point? Or that RegWrite is low for the first half a cycle? Everything including the control signal is ready to go sitting in the MEM/WB pipeline register when the clock rises. – Erik Eidt Sep 23 '22 at 15:48
  • See article plz, there is something new – Mr.Knife Sep 23 '22 at 15:55

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