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I have a CPU with the following infos:

Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                48
On-line CPU(s) list:   0-47
Thread(s) per core:    2
Core(s) per socket:    12
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 63
Model name:            Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz
Stepping:              2
CPU MHz:               3185.729
CPU max MHz:           3300.0000
CPU min MHz:           1200.0000
BogoMIPS:              4999.97
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              30720K
NUMA node0 CPU(s):     0-11,24-35
NUMA node1 CPU(s):     12-23,36-47
Flags:                 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm epb intel_ppin ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm xsaveopt cqm_llc cqm_occup_llc dtherm ida arat pln pts md_clear spec_ctrl intel_stibp flush_l1d

When I use pytorch to test the performance of GEMM with a single thread on this CPU, it reports a performance of ~40 GFlops. As shown in the cpu information, this cpu supports only fma instruction set (not avx512) which maybe used to tune GEMM kernels. I failed to find the exact multiply and accumulate instruction used in Pytorch. I assume that GEMM kernel use _mm256_fmadd_ps to optimize their code. But this instruction may have a thoughput of 0.5 per cycle (as metioned in https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=FMA&text=_mm256_fmadd_ps&ig_expand=5264,3206), i.e., (0.5*256/32=4) fma options per cycle. Thus, we have a thoery performance of GEMM 3.3 * 4 Gflops < 40Gflops.

Why?

aban
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  • 8 floats per vector x 2 vectors per clock x 2 FLOPs per FMA is a theoretical max FLOPs of 32/clock per core, or 105.6GFLOP/s per core. I think you're misreading the reciprocal throughput of 0.5, it means 1 per 0.5 cycles. And you forgot that an FMA counts as a mul and an add for the purposes of FLOPs, according to the usual conventions. – Peter Cordes Oct 12 '22 at 05:39

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